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公开(公告)号：US09946815B1
公开(公告)日：2018-04-17
申请号：US14094464
申请日：2013-12-02
Applicant: Google Inc.
Inventor： Wolf-Dietrich Weber , Xiaobo Fan , Luiz Andre Barroso
CPC classification number: G06F17/5009 , G06F1/00 , G06F1/3206 , G06F9/5094 , Y02D10/22
Abstract: A method for use in deploying computers into a data center includes calculating in a computer an expected peak power draw for a plurality of computers. The expected peak power draw for the plurality of computers is less than a sum of individual expected peak power draws for each computer from the plurality of computers.
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公开(公告)号：US09563216B1
公开(公告)日：2017-02-07
申请号：US14084835
申请日：2013-11-20
Applicant: Google Inc.
Inventor： Luiz Andre Barroso , Christopher G. Malone , Taliver Brooks Heath , Nathaniel Edward Pettis , Stephanie Hua Taylor , Michael C. Ryan
CPC classification number: G05F1/66
Abstract: Techniques for managing power loads of a data center include electrically coupling a data center infrastructure power load and a data center IT power load in a power distribution system having a specified power capacity, the infrastructure power load including a plurality of infrastructure power loads associated with at least one of a data center cooling system, a data center lighting system, or a data center building management system, and the IT power load including a plurality of IT power loads associated with a plurality of rack-mounted computing devices; determining that a predicted amount of the IT power load is about equal to or greater than a threshold power value; throttling the infrastructure power load to reduce a portion of the power capacity used by the infrastructure power load; and based on throttling the infrastructure power load, increasing another portion of the power capacity available to the IT power load.
Abstract translation: 用于管理数据中心的电力负载的技术包括将数据中心基础设施电力负载和数据中心IT电力负载电耦合到具有指定功率容量的配电系统中，该基础设施电力负载包括与之相关联的多个基础设施电力负载 数据中心冷却系统，数据中心照明系统或数据中心建筑物管理系统中的至少一个以及包括与多个机架式计算设备相关联的多个IT电力负载的IT电力负载; 确定IT功率负载的预测量大约等于或大于阈值功率值; 节省基础设施电力负载，以减少基础设施电力负荷使用的一部分电力容量; 并且基于节省基础设施电力负载，增加IT电力负载可用的电力容量的另一部分。
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公开(公告)号：US20170017611A1
公开(公告)日：2017-01-19
申请号：US14854787
申请日：2015-09-15
Applicant: Google Inc.
Inventor： Luiz Andre Barroso
IPC: G06F15/80
CPC classification number: G06F15/80 , G06F9/5061
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing processor latency through the use of dedicated cores. In one aspect, a method includes a multi-core processor having n cores, including, selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, m cores are unselected, and each core of the multi-core processor has a rated core capacity. The methods operate the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity and operate one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.
Abstract translation: 方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于通过使用专用核来减少处理器等待时间。 一方面，一种方法包括具有n个核的多核处理器，包括选择多核处理器的n个核的k个核以对n核处理器执行专用的低等待时间操作，其中k小于 n，m个磁芯未选择，多核处理器的每个核心具有额定的核心容量。 这些方法以小于等于额定核心容量的方式操作所选择的k个核心，使得k个核心被未充分利用的能力共同未被充分利用，并且以超过额定核心容量的容量操作一个或多个m个核心，使得m个核心操作 集体能力超过了m个核心的额定核心容量的集体能力。
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Patent Agency Ranking
公开(公告)号：US09250999B1
公开(公告)日：2016-02-02
申请号：US14083855
申请日：2013-11-19
Applicant: GOOGLE INC.
Inventor： Luiz Andre Barroso
CPC classification number: H03M13/1515 , G06F11/1064 , G06F12/0246 , G06F13/28 , G06F13/4243
Abstract: A method includes deploying non-volatile random access memory (NVRAM) in a memory arrangement coupled to a CPU core of a computing device via a memory bus. The method further includes configuring the CPU core to conduct NVRAM read operations directly over the memory bus, and providing an I/O logic device to process write instructions initiated by the CPU core as a Direct Memory Access (DMA) write operation on the NVRAM.
Abstract translation: 一种方法包括在经由存储器总线耦合到计算设备的CPU核心的存储器配置中部署非易失性随机存取存储器（NVRAM）。 该方法还包括配置CPU内核以直接在存储器总线上进行NVRAM读取操作，以及提供I / O逻辑器件来处理由CPU内核发起的写入指令，作为对NVRAM的直接存储器访问（DMA）写入操作。
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公开(公告)号：US09779058B2
公开(公告)日：2017-10-03
申请号：US14854787
申请日：2015-09-15
Applicant: Google Inc.
Inventor： Luiz Andre Barroso
CPC classification number: G06F15/80 , G06F9/5061
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing processor latency through the use of dedicated cores. In one aspect, a method includes a multi-core processor having n cores, including, selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, m cores are unselected, and each core of the multi-core processor has a rated core capacity. The methods operate the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity and operate one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.
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公开(公告)号：US09384036B1
公开(公告)日：2016-07-05
申请号：US14059218
申请日：2013-10-21
Applicant: Google Inc.
Inventor： Luiz Andre Barroso , James Laudon , Michael R. Marty
CPC classification number: G06F9/461 , G06F9/3009 , G06F9/30123 , G06F9/3851 , G06F12/0815 , G06F2212/451
Abstract: A method includes performing one or more operations as requested by a thread executing on a processor, the thread having a thread context; receiving a park request from the thread, the park request received following a request from the thread for a low latency resource, wherein the cache response time is less than or equal to a resource response threshold so as to allow the thread context to be stored and retrieved from the cache in less time than the portion of time it takes to complete the request for the low latency resource; storing the thread context in the cache; detecting that the resume condition has occurred; retrieving the thread context from the cache; and resuming execution of the thread.
Abstract translation: 一种方法包括：执行在处理器上执行的线程所请求的一个或多个操作，所述线程具有线程上下文; 从所述线程接收到驻留请求，所述驻留请求是在所述线程针对低延迟资源的请求之后接收的，其中所述高速缓存响应时间小于或等于资源响应阈值，以便允许所述线程上下文被存储;以及 从比缓存时间资源完成请求所花费的时间少的时间，从缓存中检索; 将线程上下文存储在高速缓存中; 检测到恢复条件已经发生; 从缓存中检索线程上下文; 并恢复线程的执行。
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公开(公告)号：US09218310B2
公开(公告)日：2015-12-22
申请号：US13835000
申请日：2013-03-15
Applicant: GOOGLE INC.
Inventor： Luiz Andre Barroso , James Laudon
CPC classification number: G06F13/4045 , G06F13/38 , G06F13/382 , G06F2213/0026
Abstract: A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.
Abstract translation: 系统包括总线，可操作地耦合到总线的处理器，可操作地耦合到总线的存储器，可操作地耦合到总线的多个输入/输出（I / O）设备，其中每个I / O设备具有 一组控制寄存器，以及可操作地耦合到总线的第一共享I / O单元。 第一共享I / O单元具有多个共享功能，并且被配置为执行共享功能，其中共享I / O功能不包括在I / O设备和I / O设备和处理器相互作用之间的功能中 第一共享I / O单元使用由第一共享I / O单元执行的一个或多个共享功能。
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公开(公告)号：US20140281107A1
公开(公告)日：2014-09-18
申请号：US13835000
申请日：2013-03-15
Applicant: GOOGLE INC.
Inventor： Luiz Andre Barroso , James Laudon
IPC: G06F13/40
CPC classification number: G06F13/4045 , G06F13/38 , G06F13/382 , G06F2213/0026
Abstract: A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.
Abstract translation: 系统包括总线，可操作地耦合到总线的处理器，可操作地耦合到总线的存储器，可操作地耦合到总线的多个输入/输出（I / O）设备，其中每个I / O设备具有 一组控制寄存器，以及可操作地耦合到总线的第一共享I / O单元。 第一共享I / O单元具有多个共享功能，并且被配置为执行共享功能，其中共享I / O功能不包括在I / O设备和I / O设备和处理器相互作用之间的功能中 第一共享I / O单元使用由第一共享I / O单元执行的一个或多个共享功能。
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