公开(公告)号：US12027449B2

公开(公告)日：2024-07-02

申请号：US17974794

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Hossein Mousavian ,  Edward Macrobbie

IPC: H01L29/417 ,  H01L23/482 ,  H01L29/20 ,  H01L29/778 ,  H01L29/861

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L29/8611

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

公开(公告)号：US12107416B2

公开(公告)日：2024-10-01

申请号：US17975092

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Edward Macrobbie

IPC: H02H9/00 ,  H01L27/02 ,  H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0288

Abstract: A GaN semiconductor power switching device (Qmain) comprising an integrated ESD 1protection circuit is disclosed, which is compatible with driving Qmain with a positive gate-to-source voltage Vgs for turn-on and a negative Vgs for turn-off, during normal operation. The ESD protection circuit is connected between a gate input of Qmain and a source of Qmain, and comprises a clamp transistor Q1, a positive trigger circuit and a negative trigger circuit, for turning on the gate of the clamp transistor Q1 responsive to an ESD event at the gate input of Qmain. The positive and negative trigger circuits each comprise a plurality of diode elements in series, having threshold voltages which are configured so that each of the positive trigger voltage and the negative trigger voltage can be adjusted. The ESD circuit topology requires smaller integrated resistors and can be implemented with reduced layout area compared to conventional integrated ESD circuits.

公开(公告)号：US12040257B2

公开(公告)日：2024-07-16

申请号：US17974880

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Edward Macrobbie

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/7786

Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a center of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.