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    Guard cell for etching
    3.
    发明授权
    Guard cell for etching 失效
    保护电池用于蚀刻

    公开(公告)号：US6060398A

    公开(公告)日：2000-05-09

    申请号：US37288

    申请日：1998-03-09

    申请人： Axel Christoph Brintzinger ,  Ravikumar Ramachandran ,  Senthil Kumar Srinivasan

    发明人： Axel Christoph Brintzinger ,  Ravikumar Ramachandran ,  Senthil Kumar Srinivasan

    IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L23/525

    CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L23/5256 ,  H01L2924/0002

    摘要： A method and apparatus for protecting a neighboring area that is adjacent to a first area that is to be etched. The method includes creating a guard cell substantially surrounding the first area, but excluding the neighboring area. The guard cell is formed of a material that is substantially selective to the etch process subsequently employed to etch within the first area. After the guard cell is formed, an etch is performed within the first area, while the guard cell prevents etching of the neighboring are outside the guard cell.

    摘要翻译： 一种用于保护与待蚀刻的第一区域相邻的相邻区域的方法和装置。 该方法包括创建基本上围绕第一区域但不包括相邻区域的保护单元。 保护电池由对第一区域中随后用于蚀刻的蚀刻工艺基本选择性的材料形成。 在形成保护单元之后，在第一区域内执行蚀刻，而保护单元防止相邻的蚀刻在保护单元之外。

    Area efficient stacking of antifuses in semiconductor device
    5.
    发明授权
    Area efficient stacking of antifuses in semiconductor device 有权
    半导体器件中反熔丝的区域有效堆叠

    公开(公告)号：US07087975B2

    公开(公告)日：2006-08-08

    申请号：US09751474

    申请日：2000-12-28

    申请人： Gunther Lehmann ,  Axel Christoph Brintzinger ,  Gabriel Daniel

    发明人： Gunther Lehmann ,  Axel Christoph Brintzinger ,  Gabriel Daniel

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.

    摘要翻译： 提供一种半导体器件，其由具有在其表面上的垂直堆叠关系中的至少两个反熔丝的区域有效布置的晶片形成，并且在其间共享公共中间电极。 该装置包括至少一个下部反熔丝，其具有下部对电极和下部可熔绝缘体部分，该熔断绝缘体部分限定了将下部反电极与公共中间电极互连的初始高电阻状态的下部熔丝元件，以及至少一个上部反熔丝， 其可以与下部反熔丝相同或不同，上部反熔丝具有上部对电极和上部可熔绝缘体部分，其限定具有初始高电阻状态的上部熔丝元件，其将上部对置电极与公共中间电极 。

    Chip crack stop design for semiconductor chips
    7.
    发明授权
    Chip crack stop design for semiconductor chips 有权
    半导体芯片的芯片裂纹停止设计

    公开(公告)号：US06495918B1

    公开(公告)日：2002-12-17

    申请号：US09655461

    申请日：2000-09-05

    申请人： Axel Christoph Brintzinger

    发明人： Axel Christoph Brintzinger

    IPC分类号： H01L2348

    CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive line disposed over the substrate and at least two first contacts connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the first conductive line and the second conductive line. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the second conductive line.

    摘要翻译： 根据本发明的半导体芯片包括基板和裂纹停止结构。 裂纹结构包括设置在衬底上的第一导电线和连接到衬底和第一导电线的至少两个第一触点。 所述至少两个第一触点彼此间隔开并沿着第一导线的长度纵向延伸。 第二导线设置在第一导线的一部分上，并且至少两个第二触点连接到第一导线和第二导线。 所述至少两个第二触点彼此间隔开并沿着所述第二导线的长度纵向地延伸。