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公开(公告)号：US07471623B2
公开(公告)日：2008-12-30
申请号：US10998239
申请日：2004-11-23
申请人： Gary B. Gostin , Craig Warner , John W. Bockhaus
发明人： Gary B. Gostin , Craig Warner , John W. Bockhaus
IPC分类号： H04L1/00
CPC分类号： G06F13/4022
摘要： Disclosed are systems and methods providing a unified system fabric in a computer. The systems and methods of embodiments including first interface disposed between a first component of the computer system and a second component of the computer system, the first interface implementing an interface protocol, and a second interface disposed between the first component of the computer system and a third component of the computer system, the second interface implementing the interface protocol, wherein the first interface and the second interface comprise separate signal paths at the first component.
摘要翻译： 公开了在计算机中提供统一的系统结构的系统和方法。 实施例的系统和方法包括设置在计算机系统的第一部件和计算机系统的第二部件之间的第一接口，实现接口协议的第一接口和设置在计算机系统的第一部件之间的第二接口和 计算机系统的第三组件，实现接口协议的第二接口，其中第一接口和第二接口在第一组件处包括单独的信号路径。
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公开(公告)号：US08225048B2
公开(公告)日：2012-07-17
申请号：US12432348
申请日：2009-04-29
申请人： Gregg B. Lesartre , Craig Warner , John Wastlick , Harvey Ray , John W. Bockhaus
发明人： Gregg B. Lesartre , Craig Warner , John Wastlick , Harvey Ray , John W. Bockhaus
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged.
摘要翻译： 提供系统和方法来管理对计算资源的访问。 更具体地，描述某些实施例，其中如果请求的年龄超过一个或多个阈值，资源或资源消费者可以参与访问控制或请求访问控制被接合。 例如，请求者可以在请求的年龄满足或超过阈值之后向目的地指示应当控制控制。
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公开(公告)号：US20110179423A1
公开(公告)日：2011-07-21
申请号：US13122331
申请日：2008-10-02
申请人： Gregg B. Lesartre , Craig Warner , Gary Gostin , John W. Bockhaus
发明人： Gregg B. Lesartre , Craig Warner , Gary Gostin , John W. Bockhaus
IPC分类号： G06F9/50
CPC分类号： G06F15/173
摘要： In a computing system having a plurality of transaction source nodes issuing transactions into a switching fabric, an underserviced node notifies source nodes in the system that it needs additional system bandwidth to timely complete an ongoing transaction. The notified nodes continue to process already started transactions to completion, but stop the introduction of new traffic into the fabric until such time as the underserviced node indicates that it has progressed to a preselected point.
摘要翻译： 在具有将事务发送到交换结构中的多个事务源节点的计算系统中，欠授权节点通知系统中的源节点需要额外的系统带宽以及时完成正在进行的事务。 所通知的节点继续处理已经开始的事务完成，但是停止将新流量引入到结构中，直到欠观察节点指示它已经进展到预先选择的点为止。
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公开(公告)号：US08000322B2
公开(公告)日：2011-08-16
申请号：US11079414
申请日：2005-03-14
申请人： James R. Greener , Christopher P. Woody , Robert McFarland , Tyler J. Johnson , Gregg Bernard Lesartre , John W. Bockhaus
发明人： James R. Greener , Christopher P. Woody , Robert McFarland , Tyler J. Johnson , Gregg Bernard Lesartre , John W. Bockhaus
IPC分类号： H04L12/50
CPC分类号： G06F11/221
摘要： A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status information.
摘要翻译： 具有多个端口的交叉开关，其允许使用所述多个端口中的一个来对所述交换机执行调试处理以输出芯片状态信息。 交换机使用调试块来存储芯片状态信息。
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公开(公告)号：US20110246833A1
公开(公告)日：2011-10-06
申请号：US13133314
申请日：2008-12-15
IPC分类号： G06F11/07
CPC分类号： H04L43/0847 , H04L43/16
摘要： One embodiment of a system for analyzing reliability of a communication link comprises a link control component that controls the communication link, where the link control component couples to a processor and a diagnostic component. The diagnostic component is configured to determine whether transmission errors have occurred on the communication link exceeding or matching a first programmable threshold over a range of multiple periods of time that exceeds or matches a second programmable threshold.
摘要翻译： 用于分析通信链路的可靠性的系统的一个实施例包括控制通信链路的链路控制组件，其中链路控制组件耦合到处理器和诊断部件。 诊断部件被配置为确定在超过或匹配于第二可编程阈值的多个时间段的范围内超过或匹配第一可编程阈值的通信链路上是否发生传输错误。
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6.发明授权Circuitry for providing external access to signals that are internal to an integrated circuit chip package 失效用于提供对集成电路芯片封装内部信号的外部访问的电路
公开(公告)号：US6003107A
公开(公告)日：1999-12-14
申请号：US707936
申请日：1996-09-10
CPC分类号： G06F7/02
摘要： Circuitry for providing external access to signals that are internal to an integrated circuit chip package. A plurality of N:1 multiplexers are physically distributed throughout the integrated circuit die. Each of the multiplexers has its N inputs coupled to a nearby set of N nodes within the integrated circuit, and each of the multiplexers is coupled to a source of select information operable to select one node from the set of N nodes for external access. Each of the multiplexers has its output coupled to an externally-accessible chip pad. The integrated circuit is a microprocessor, and the source of select information may include a storage element. If so, additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions. Each multiplexer may be coupled to a different source of select information, or all multiplexers may be coupled to the same select information. Moreover, a fixed set of interconnect traces may be provided to couple a fixed set of nodes to an additional set of externally-accessible chip pads. One or more M:1 multiplexers may also be provided, having their M inputs coupled to M different outputs of the N:1 multiplexers. Each of the M:1 multiplexers may be coupled to a second source of select information. Preferably, the outputs of the M:1 multiplexers will be coupled to a circuitry for facilitating debug and performance monitoring of the integrated circuit.
摘要翻译： 用于提供对集成电路芯片封装内部信号的外部访问的电路。 多个N：1复用器物理地分布在整个集成电路管芯中。 每个复用器具有其N个输入耦合到集成电路内的附近的一组N个节点，并且每个多路复用器耦合到可选择信息的源，用于从用于外部访问的N个节点的集合中选择一个节点。 每个多路复用器的输出耦合到外部可访问的芯片焊盘。 集成电路是微处理器，选择信息的源可以包括存储元件。 如果是这样，则提供附加电路用于使用一个或多个微处理器指令将数据从微处理器的寄存器写入存储元件。 每个复用器可以耦合到不同的选择信息源，或者所有复用器可以耦合到相同的选择信息。 此外，可以提供固定的一组互连轨迹以将固定的一组节点耦合到另外一组外部可访问的芯片焊盘。 还可以提供一个或多个M：1多路复用器，其M个输入端耦合到N：1多路复用器的M个不同输出。 M：1多路复用器中的每一个可以耦合到第二选择信息源。 优选地，M：1多路复用器的输出将耦合到用于促进集成电路的调试和性能监视的电路。
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7.发明授权System and method for on-chip debug support and performance monitoring in a microprocessor 失效用于微处理器中片上调试支持和性能监控的系统和方法
公开(公告)号：US5867644A
公开(公告)日：1999-02-02
申请号：US711491
申请日：1996-09-10
申请人： Gregory L. Ranson , John W. Bockhaus , Gregg B. Lesartre , Russell C. Brockmann , Robert E. Naas , Jonathan P. Lotz , Douglas B. Hunt , Patrick Knebel , Paul L. Perez , Steven T. Mangelsdorf
发明人： Gregory L. Ranson , John W. Bockhaus , Gregg B. Lesartre , Russell C. Brockmann , Robert E. Naas , Jonathan P. Lotz , Douglas B. Hunt , Patrick Knebel , Paul L. Perez , Steven T. Mangelsdorf
CPC分类号： G06F11/3648 , G06F11/364
摘要： User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements. By changing data in the storage elements, the programmer may change the information against which the state of the nodes is compared and also the method by which the comparison is made. The output devices include counters. Counter outputs may be used as state machine inputs, so one event may be defined as a function of a different event having occurred a certain number of times. The output devices also include circuitry for generating internal and external triggers. User-configurable multiplexer circuitry may be used to route user-selectable signals from within the microprocessor to the chip's output pads, and to select various internal signals to be used as state machine inputs.
摘要翻译： 用户可配置的诊断硬件包含微处理器，用于调试和监视微处理器的性能。 使用方法 可编程状态机耦合到片上和片外输入源。 状态机可以被编程为寻找由输入源呈现的信号模式，并且通过将某些控制信息驱动到状态机输出总线上来响应定义的模式（或定义的模式的序列）的出现。 耦合到输出总线的片上设备采用由总线指示的用户可定义的动作。 输入源包括位于微处理器的功能块内的用户可配置比较器。 比较器耦合到微处理器内的存储元件，并且被配置为监视节点以确定节点的状态是否与包含在存储元件中的数据匹配。 通过改变存储元件中的数据，程序员可以改变比较节点状态的信息，以及进行比较的方法。 输出设备包括计数器。 计数器输出可以用作状态机输入，因此可以将一个事件定义为发生一定次数的不同事件的功能。 输出设备还包括用于产生内部和外部触发的电路。 用户可配置的多路复用器电路可以用于将用户可选择的信号从微处理器传送到芯片的输出焊盘，并且选择要用作状态机输入的各种内部信号。
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公开(公告)号：US07721159B2
公开(公告)日：2010-05-18
申请号：US11056505
申请日：2005-02-11
IPC分类号： G06F11/00
CPC分类号： G06F11/3632 , G06F11/3648
摘要： A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.
摘要翻译： 采用串行化器和解串器的数据通信架构可以减少数据通信延迟。 在说明性实现中，数据通信架构通过通信链路传送数据。 该架构维护各种机制，以提升数据通信速度，避免通信链路停机。 这些机制执行包括但不限于生成处理调试信息，处理链路识别信息，跨通信链路注入错误并执行错误检测的功能。
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9.发明授权Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cache 失效在顺序访问微处理器的指令高速缓存时节省微处理器电力的方法和装置公开(公告)号：US06944714B2
公开(公告)日：2005-09-13
申请号：US10209473
申请日：2002-07-30
申请人： Gregg B. Lesarte , John W. Bockhaus
发明人： Gregg B. Lesarte , John W. Bockhaus
CPC分类号： G06F12/0882 , G06F1/3225 , G06F1/3275 , G06F9/3802 , G06F12/0864 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： An embodiment of the invention provides a circuit and method for reducing power in multi-way set associative arrays. A control circuit detects when the next cache access will be taken from the same cache way that the previous cache access was taken from. If the next cache access is taken from the same cache way as the previous cache access, the control circuit signals all the cache ways, except the cache way that was previously accessed, to not access information from their arrays. The control circuit also signals the tag arrays to not access their information and disables power to all the compare circuits. In this manner, power may be reduced when sequentially accessing information from one cache way in a multi-way set associative array.
摘要翻译： 本发明的一个实施例提供了一种减少多路组相关阵列功率的电路和方法。 控制电路检测下一个高速缓存访问将是从与之前的高速缓存访问相同的高速缓存方式获取的。 如果下一个高速缓存访问与先前的高速缓存访问相同的高速缓存访问，控制电路将所有高速缓存路径（除先前访问的缓存方式）信号从不从其阵列访问信息。 控制电路还向标签阵列发出信号，以不访问其信息，并禁止所有比较电路的电源。 以这种方式，当以多路组合关联阵列从一个高速缓存方式顺序访问信息时，可以减少功率。
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10.发明授权
公开(公告)号：US5880671A
公开(公告)日：1999-03-09
申请号：US742193
申请日：1996-10-31
CPC分类号： G06F11/364 , G06F11/3648 , G06F7/02
摘要： Circuitry for detecting signal patterns on a multi-bit bus. First comparison circuitry monitors a first portion of the bus comparing it with a first expected signal pattern, generating a first comparison output. Second comparison circuitry monitors a second portion of the bus comparing it with a second expected signal pattern, generating a second comparison output. Both comparison outputs are applied to an AND gate and a first OR gate. One data input of a multiplexer is coupled to the output of the first OR gate. Another data input is coupled to the output of the AND gate. Another data input is coupled to the first comparison output, and another data input is coupled to the second comparison output.One input of a second OR gate may be coupled to the multiplexer output, and another input coupled to a disable indicator, allowing the multiplexer output to be overridden. The first and second comparison outputs may be generated by bit-wise comparing first and second portions of the bus with first and second expected signal patterns. The logical AND of the respective comparison results may be treated as the first and second comparison outputs, or they may be treated as first and second intermediate bits. These first and second intermediate bits may be ORed with first and second mask bits, and the results may be treated as the first and second comparison outputs. The outputs of the two OR operations may also be EXCLUSIVE ORed with first and second negate bits, respectively.
摘要翻译： 用于检测多位总线上的信号模式的电路。 第一比较电路监视总线的第一部分，将其与第一预期信号模式相比较，产生第一比较输出。 第二比较电路监视总线的第二部分，将其与第二预期信号模式相比较，产生第二比较输出。 两个比较输出都施加到与门和第一或门。 多路复用器的一个数据输入耦合到第一或门的输出。 另一个数据输入耦合到与门的输出。 另一数据输入耦合到第一比较输出，另一数据输入耦合到第二比较输出。 第二或门的一个输入可以耦合到多路复用器输出，另一个输入耦合到禁用指示符，允许多路复用器输出被覆盖。 第一和第二比较输出可以通过比较第一和第二预期信号模式来比较总线的第一和第二部分来产生。 各个比较结果的逻辑“与”可被视为第一和第二比较输出，或者它们可被视为第一和第二中间位。 这些第一和第二中间位可以与第一和第二屏蔽位进行“或”运算，并且结果可被视为第一和第二比较输出。 两个OR运算的输出也可以分别与第一和第二否定位独占或。
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