Systems and methods for resource access
    1.
    发明授权
    Systems and methods for resource access 有权
    资源访问的系统和方法

    公开(公告)号:US08225048B2

    公开(公告)日:2012-07-17

    申请号:US12432348

    申请日:2009-04-29

    IPC分类号: G06F12/00

    CPC分类号: G06F13/1642

    摘要: Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged.

    摘要翻译: 提供系统和方法来管理对计算资源的访问。 更具体地,描述某些实施例,其中如果请求的年龄超过一个或多个阈值,资源或资源消费者可以参与访问控制或请求访问控制被接合。 例如,请求者可以在请求的年龄满足或超过阈值之后向目的地指示应当控制控制。

    System and Method for Achieving Cache Coherency Within Multiprocessor Computer System
    3.
    发明申请
    System and Method for Achieving Cache Coherency Within Multiprocessor Computer System 审中-公开
    在多处理器计算机系统中实现缓存一致性的系统和方法

    公开(公告)号:US20080270708A1

    公开(公告)日:2008-10-30

    申请号:US11741858

    申请日:2007-04-30

    IPC分类号: G06F12/08

    摘要: A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches.

    摘要翻译: 公开了一种用于在具有多个具有处理设备和存储器控制器以及多个存储器块的套接字的多处理器计算机系统中实现高速缓存一致性的系统和方法。 在至少一些实施例中,系统包括能够分别耦合到多处理器计算机的相应插槽的多个节点控制器,分别耦合到相应节点控制器的多个高速缓存设备,以及耦合各个节点控制器的结构, 由此可以在相应的节点控制器之间传送高速缓存行请求信号。 尽管至少部分地由于节点控制器与节点控制器所耦合的相应的高速缓存设备之间的通信而在各个节点控制器之间传送高速缓存行请求信号,仍然实现了高速缓存一致性。 在至少一些实施例中,缓存设备跟踪用于处理器和/或输入/输出集线器高速缓存的远程高速缓存行所有权。

    Resample and composite engine for real-time volume rendering
    6.
    再颁专利
    Resample and composite engine for real-time volume rendering 失效
    重采样和复合引擎进行实时体绘制

    公开(公告)号:USRE42638E1

    公开(公告)日:2011-08-23

    申请号:US11305902

    申请日:2005-12-16

    IPC分类号: G06T15/00

    摘要: The present invention is a digital electronic system for rendering a volume image in real time. The system accelerators the processing of voxels through early ray termination and space leaping techniques in the projection guided ray casting of the voxels. Predictable and regular voxel access from high-speed internal memory further accelerates the volume rendering. Through the acceleration techniques and devices of the present invention real-time rendering of parallel and perspective views, including those for stereoscopic viewing, are achieved.

    摘要翻译: 本发明是用于实时渲染体积图像的数字电子系统。 该系统通过早期射线终止和体素的投影引导射线投射中的空间跳跃技术来加速体素的处理。 来自高速内部存储器的可预测和常规体素访问进一步加快了体积渲染。 通过本发明的加速技术和装置,实现了平行和透视图的实时渲染,包括用于立体观看的视图。

    METHOD TO IMPROVE OPERATING PERFORMANCE OF A COMPUTING DEVICE
    7.
    发明申请
    METHOD TO IMPROVE OPERATING PERFORMANCE OF A COMPUTING DEVICE 有权
    提高计算机设备运行性能的方法

    公开(公告)号:US20100082858A1

    公开(公告)日:2010-04-01

    申请号:US12243420

    申请日:2008-10-01

    IPC分类号: G06F13/00

    CPC分类号: G06F12/0831

    摘要: The system includes a microprocessor, a first buffer, a second buffer, and a control circuit. The control circuit includes a memory and an interface. The control circuit is configured to determine a first buffer value and compare the first buffer value to a predetermined value to obtain a result. The control circuit is further configured to control a read issue rate of the first buffer based on the result. The memory is configured to store at least one of the first buffer value, the result, the read issue rate, and the TAG.

    摘要翻译: 该系统包括微处理器,第一缓冲器,第二缓冲器和控制电路。 控制电路包括存储器和接口。 控制电路被配置为确定第一缓冲器值并将第一缓冲器值与预定值进行比较以获得结果。 控制电路还被配置为基于结果来控制第一缓冲器的读取发布率。 存储器被配置为存储第一缓冲器值,结果,读发布率和TAG中的至少一个。

    MANAGING A SET OF RESOURCES
    9.
    发明申请
    MANAGING A SET OF RESOURCES 审中-公开
    管理一套资源

    公开(公告)号:US20130263148A1

    公开(公告)日:2013-10-03

    申请号:US13438357

    申请日:2012-04-03

    IPC分类号: G06F9/46

    摘要: In one example, a controller for managing a set of resources. A first structure has a first entry statically associated with one of the resources. A second structure has a second entry dynamically associative with one of the resources. A resource sharing mechanism borrows for the second structure an idle resource associated with the first structure.

    摘要翻译: 在一个示例中,用于管理一组资源的控制器。 第一结构具有与资源之一静态关联的第一条目。 第二结构具有与资源之一动态关联的第二条目。 资源共享机制借用第二结构与第一结构相关联的空闲资源。

    Method to improve operating performance of a computing device
    10.
    发明授权
    Method to improve operating performance of a computing device 有权
    提高计算设备运行性能的方法

    公开(公告)号:US08019920B2

    公开(公告)日:2011-09-13

    申请号:US12243420

    申请日:2008-10-01

    IPC分类号: G06F3/00

    CPC分类号: G06F12/0831

    摘要: The system includes a microprocessor, a first buffer, a second buffer, and a control circuit. The control circuit includes a memory and an interface. The control circuit is configured to determine a first buffer value and compare the first buffer value to a predetermined value to obtain a result. The control circuit is further configured to control a read issue rate of the first buffer based on the result. The memory is configured to store at least one of the first buffer value, the result, the read issue rate, and the TAG.

    摘要翻译: 该系统包括微处理器,第一缓冲器,第二缓冲器和控制电路。 控制电路包括存储器和接口。 控制电路被配置为确定第一缓冲器值并将第一缓冲器值与预定值进行比较以获得结果。 控制电路还被配置为基于结果来控制第一缓冲器的读取发布率。 存储器被配置为存储第一缓冲器值,结果,读发布率和TAG中的至少一个。