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    High performance digital electronic system architecture and memory circuit therefor
    2.
    发明授权
    High performance digital electronic system architecture and memory circuit therefor 失效
    高性能数字电子系统架构及其存储电路

    公开(公告)号：US6167491A

    公开(公告)日：2000-12-26

    申请号：US35640

    申请日：1998-03-05

    申请人： Gary L. McAlpine

    发明人： Gary L. McAlpine

    IPC分类号： G06F13/16 ,  G11C7/10 ,  G06F12/02

    CPC分类号： G11C7/103 ,  G06F13/1642

    摘要： A digital electronic system architecture having one or more system components and a memory coupled to selected system components, the memory selectively storing and communicating data among the coupled components. The digital electronic system preferably also has a transaction control bus, coupled to each of the selected system components and to the memory, for communicating command and control signals among the components and memory. A memory circuit is provided that has a plurality of ports, each of the ports (i) having an input terminal and an output terminal that transfer data independently of one another, (ii) operating independently of one another and (iii) being coupled respectively to one of the other system components for data communication therewith. A read interface for a memory array is provided that has a queue for receiving data read from a row of the array and a selection circuit for placing in the queue a contiguous block of the read data, the size of the block and its placement being selectable. The read interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable blocks of the read data in independently selectable positions in selected queues. A write interface for a memory array is also provided that has a queue for receiving data to be written to the array and a selection circuit for placing in the array a contiguous block of received data, the size of the block and its placement being selectable. The write interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable data received from selected queues in independently selectable positions in the memory array.

    摘要翻译： 一种具有一个或多个系统组件的数字电子系统架构和耦合到所选择的系统组件的存储器，所述存储器选择性地在所耦合的组件之间存储和传送数据。 数字电子系统优选地还具有耦合到所选择的系统组件中的每一个和存储器的事务控制总线，用于在组件和存储器之间传送命令和控制信号。 提供具有多个端口的存储器电路，每个端口（i）具有输入端子和输出端子，其彼此独立地传输数据，（ii）彼此独立地操作和（iii）分别耦合 到与其进行数据通信的其他系统组件之一。 提供了一种用于存储器阵列的读取接口，其具有用于接收从阵列的行读取的数据的队列，以及用于将读取的数据的连续块放置在队列中的选择电路，块的大小及其布置可选择 。 读取接口优选地包括多个队列，并且选择电路优选地适于将所读取的数据的独立可选块放置在所选队列中的独立可选位置。 还提供了一种用于存储器阵列的写接口，其具有用于接收要写入阵列的数据的队列和用于将阵列中的接收数据的连续块放置在阵列中的选择电路，块的大小及其布局是可选择的。 写入接口优选地包括多个队列，并且选择电路优选地适于将从选定队列接收的独立可选数据置于存储器阵列中的独立可选位置。

    Direct message transfer between distributed processes
    3.
    发明授权
    Direct message transfer between distributed processes 失效
    分布式进程之间的直接消息传输

    公开(公告)号：US06647423B2

    公开(公告)日：2003-11-11

    申请号：US09097757

    申请日：1998-06-16

    申请人： Gregory J. Regnier ,  David S. Dunning ,  Donald F. Cameron ,  Gary L. McAlpine

    发明人： Gregory J. Regnier ,  David S. Dunning ,  Donald F. Cameron ,  Gary L. McAlpine

    IPC分类号： G06F1516

    CPC分类号： G06F9/546

    摘要： An interprocess communication technique transfers a message from a first process' memory (on a first computer system) directly to a second process' memory (on a second computer system). The message is identified by a virtual address and possibly a memory handle. The message is not stored in intermediary memory, such as operating system buffer memory, during the transfer. The communication technique may also provide virtual to physical address translation and memory protection. Memory protection is provided by ensuring that the communicating processes own the memory (the contents of which includes the message) being transferred between them.

    摘要翻译： 进程间通信技术将来自第一进程的存储器（在第一计算机系统上）的消息直接传送到第二进程的存储器（在第二计算机系统上）。 消息由虚拟地址和可能的存储器句柄来标识。 在传输过程中，消息不会存储在中间存储器中，如操作系统缓冲存储器。 通信技术还可以提供虚拟到物理地址转换和存储器保护。 通过确保通信进程拥有在它们之间转移的存储器（其内容包括消息）来提供存储器保护。

    Interleaved memory addressing system and method using a parity signal
    5.
    发明授权
    Interleaved memory addressing system and method using a parity signal 失效
    交错式存储器寻址系统和使用奇偶校验信号的方法

    公开(公告)号：US4800535A

    公开(公告)日：1989-01-24

    申请号：US43840

    申请日：1987-04-28

    申请人： Gary L. McAlpine

    发明人： Gary L. McAlpine

    IPC分类号： G06F12/06 ,  G11C8/12 ,  G11C8/00 ,  G06F11/10 ,  H03M13/00

    CPC分类号： G06F12/0607 ,  G11C8/12

    摘要： A high performance interleaved memory addressing system and method. A plurality of banks of random access memory devices are provided. The appropriate bank for a given memory address is selected based upon the parity among a preselected set of address bits including the least significant bit. A parity signal for selection of a memory bank is produced by a parity signal generation circuit, preferably a logic circuit. Typically, more than two memory banks would be employed, utilizing at least two parity signal generation circuits, each corresponding to respective least significant bits of the memory address. The output signals from the parity circuits are combined in a decoder to select the memory bank.

    摘要翻译： 高性能交错存储器寻址系统和方法。 提供了多组随机存取存储器件。 基于包括最低有效位的预先选择的地址位集合之间的奇偶校验来选择给定存储器地址的适当存储体。 用于选择存储体的奇偶校验信号由奇偶校验信号生成电路产生，优选地由逻辑电路产生。 通常，将使用多于两个的存储体，利用至少两个奇偶校验信号产生电路，每个对应于存储器地址的相应的最低有效位。 来自奇偶校验电路的输出信号在解码器中组合以选择存储体。

    Directional and priority based flow control mechanism between nodes
    6.
    发明授权
    Directional and priority based flow control mechanism between nodes 有权
    节点之间的基于定向和优先级的流控制机制

    公开(公告)号：US07903552B2

    公开(公告)日：2011-03-08

    申请号：US12276207

    申请日：2008-11-21

    申请人： Gary L. McAlpine ,  Tanmay Gupta ,  Manoj K. Wadekar

    发明人： Gary L. McAlpine ,  Tanmay Gupta ,  Manoj K. Wadekar

    IPC分类号： H04L1/00

    CPC分类号： H04L47/20 ,  H04L47/10 ,  H04L47/125 ,  H04L47/2441 ,  H04L47/26 ,  H04L47/30 ,  H04L47/6215

    摘要： A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion.

    摘要翻译： 节点使用发射队列的二维阵列来存储要从节点发送到另一个节点的帧。 阵列的大小由另一个节点可以一旦从节点接收到的帧转发的方向的数量以及可能与帧相关联的优先级的数量来控制。 基于方向和优先级将发送队列彼此区分开。 发射机将发送队列出队的帧发送到另一个节点。 控制发送队列的控制逻辑从另一个节点接收指示，否则其他节点正在任何方向上经历业务拥塞，以及控制逻辑要控制从对应于发送队列的帧出队的帧的优先级 到另一个节点遇到交通拥堵的方向。

    Embedded transport acceleration architecture
    7.
    发明授权
    Embedded transport acceleration architecture 有权
    嵌入式传输加速架构

    公开(公告)号：US07305493B2

    公开(公告)日：2007-12-04

    申请号：US10305738

    申请日：2002-11-27

    申请人： Gary L. McAlpine ,  David B. Minturn ,  Hemal V. Shah ,  Annie Foong ,  Greg J. Regnier ,  Vikram A. Saletore

    发明人： Gary L. McAlpine ,  David B. Minturn ,  Hemal V. Shah ,  Annie Foong ,  Greg J. Regnier ,  Vikram A. Saletore

    IPC分类号： G06F15/16 ,  G06F13/00 ,  G06F13/42 ,  H04L12/28 ,  G06F9/46 ,  G06F3/00 ,  G06F13/36 ,  H04L12/56

    CPC分类号： G06F9/543 ,  H04L69/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/162 ,  H04L69/163 ,  H04L69/32

    摘要： An apparatus and a system may include an adaptation module, a plurality of Direct Transport Interfaces (DTIs), a DTI accelerator, and a Transport Control Protocol/Internet Protocol (TCP/IP) accelerator. The adaptation module may provide a translated sockets call from an application program to one of the DTIs, where an included set of memory structures may couple the translated sockets call to the DTI accelerator, which may in turn couple the set of memory structures to the TCP/IP accelerator. An article may include data causing a machine to perform a method including: receiving an application program sockets call at the adaptation module, deriving a translated sockets call from the application program sockets call, receiving the translated sockets call at a DTI, coupling the translated sockets call to a DTI accelerator using a set of memory structures in the DTI, and coupling the set of memory structures to a TCP/IP accelerator.

    摘要翻译： 装置和系统可以包括适配模块，多个直接传输接口（DTI），DTI加速器和传输控制协议/因特网协议（TCP / IP）加速器。 适配模块可以将应用程序的翻译套接字调用提供给DTI之一，其中所包含的一组存储器结构可以将翻译的套接字调用耦合到DTI加速器，DTI加速器可以将该组存储器结构耦合到TCP / IP加速器。 文章可以包括导致​​机器执行方法的数据，包括：在适配模块处接收应用程序套接字呼叫，从应用程序套接字呼叫导出翻译的套接字呼叫，在DTI处接收翻译的套接字调用，将转换的套接字 使用DTI中的一组存储器结构调用DTI加速器，并将该组内存结构耦合到TCP / IP加速器。

    High performance digital electronic system architecture and memory circuit thereof
    10.
    发明授权
    High performance digital electronic system architecture and memory circuit thereof 失效
    高性能数字电子系统架构及其存储电路

    公开(公告)号：US5802580A

    公开(公告)日：1998-09-01

    申请号：US812376

    申请日：1997-03-05

    申请人： Gary L. McAlpine

    发明人： Gary L. McAlpine

    IPC分类号： G06F13/16 ,  G11C7/10 ,  G06F12/02

    CPC分类号： G11C7/103 ,  G06F13/1642

    摘要： A digital electronic system architecture having one or more system components and a memory coupled to selected system components, the memory selectively storing and communicating data among the coupled components. The digital electronic system preferably also has a transaction control bus, coupled to each of the selected system components and to the memory, for communicating command and control signals among the components and memory. A memory circuit is provided that has a plurality of ports, each of the ports (i) having an input terminal and an output terminal that transfer data independently of one another, (ii) operating independently of one another and (iii) being coupled respectively to one of the other system components for data communication therewith. A read interface for a memory array is provided that has a queue for receiving data read from a row of the array and a selection circuit for placing in the queue a contiguous block of the read data, the size of the block and its placement being selectable. The read interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable blocks of the read data in independently selectable positions in selected queues. A write interface for a memory array is also provided that has a queue for receiving data to be written to the array and a selection circuit for placing in the array a contiguous block of received data, the size of the block and its placement being selectable. The write interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable data received from selected queues in independently selectable positions in the memory array.

    摘要翻译： 一种具有一个或多个系统组件的数字电子系统架构和耦合到所选择的系统组件的存储器，所述存储器选择性地在所耦合的组件之间存储和传送数据。 数字电子系统优选地还具有耦合到所选择的系统组件中的每一个和存储器的事务控制总线，用于在组件和存储器之间传送命令和控制信号。 提供具有多个端口的存储器电路，每个端口（i）具有输入端子和输出端子，其彼此独立地传输数据，（ii）彼此独立地操作和（iii）分别耦合 到与其进行数据通信的其他系统组件之一。 提供了一种用于存储器阵列的读取接口，其具有用于接收从阵列的行读取的数据的队列，以及用于将读取的数据的连续块放置在队列中的选择电路，块的大小及其布置可选择 。 读取接口优选地包括多个队列，并且选择电路优选地适于将所读取的数据的独立可选块放置在所选队列中的独立可选位置。 还提供了一种用于存储器阵列的写接口，其具有用于接收要写入阵列的数据的队列和用于将阵列中的接收数据的连续块放置在阵列中的选择电路，块的大小及其布局是可选择的。 写入接口优选地包括多个队列，并且选择电路优选地适于将从选定队列接收的独立可选数据置于存储器阵列中的独立可选位置。