Semiconductor device having trench structures and method
    6.
    发明申请
    Semiconductor device having trench structures and method 有权
    具有沟槽结构和方法的半导体器件

    公开(公告)号:US20060261444A1

    公开(公告)日:2006-11-23

    申请号:US11132949

    申请日:2005-05-20

    IPC分类号: H01L27/082

    摘要: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

    摘要翻译: 在一个实施例中,在衬底中形成一对侧壁钝化沟槽触点以提供与子表面特征的电接触。 掺杂区域在一对侧壁钝化沟槽之间扩散,以提供低电阻触点。

    SEMICONDUCTOR DEVICE HAVING TRENCH STRUCTURES AND METHOD
    9.
    发明申请
    SEMICONDUCTOR DEVICE HAVING TRENCH STRUCTURES AND METHOD 有权
    具有TRENCH结构和方法的半导体器件

    公开(公告)号:US20080012137A1

    公开(公告)日:2008-01-17

    申请号:US11769650

    申请日:2007-06-27

    IPC分类号: H01L23/52 H01L21/44

    摘要: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

    摘要翻译: 在一个实施例中,在衬底中形成一对侧壁钝化沟槽触点以提供与子表面特征的电接触。 掺杂区域在一对侧壁钝化沟槽之间扩散,以提供低电阻触点。

    High energy ESD structure and method
    10.
    发明申请
    High energy ESD structure and method 有权
    高能ESD结构及方法

    公开(公告)号:US20050145945A1

    公开(公告)日:2005-07-07

    申请号:US10750267

    申请日:2004-01-02

    IPC分类号: H01L27/02 H01L23/62

    CPC分类号: H01L27/0255

    摘要: In one embodiment, a concentric ring ESD structure includes a first p-type region and a second p-type region are formed in a layer of semiconductor material. The two p-type regions are coupled together with a floating n-type buried layer. The first and second p-type regions form a back-to-back diode structure with the floating n-type buried layer. A pair of shorted n-type and p-type contact regions is formed in each of the first and second regions. An isolation region is formed between the first and second p-type regions.

    摘要翻译: 在一个实施例中,同心环ESD结构包括第一p型区域和第二p型区域形成在半导体材料层中。 两个p型区域与浮动n型掩埋层耦合在一起。 第一和第二p型区域形成具有浮置n型掩埋层的背对背二极管结构。 在第一和第二区域的每一个中形成一对短路的n型和p型接触区域。 在第一和第二p型区域之间形成隔离区域。