公开(公告)号：US08464099B2

公开(公告)日：2013-06-11

申请号：US12913029

申请日：2010-10-27

申请人： Gary Verdun ,  William F. Sauber

发明人： Gary Verdun ,  William F. Sauber

IPC分类号： G06F11/30

CPC分类号： G06F11/0757 ,  G06F1/26 ,  G06F11/0745

摘要： A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.

摘要翻译： 如果信息处理系统响应于正常掉电消息而断电，则强制断电信号通过光互连从I / O设备发送到信息处理系统。 100％占空比信号从I / O设备的光接口出现，并由信息处理系统的光接口检测到，该信号处理系统的光接口响应于强制功率发出强制信息处理系统断电的命令 下降信号。

公开(公告)号：US08499194B2

公开(公告)日：2013-07-30

申请号：US12952464

申请日：2010-11-23

申请人： Gary Verdun ,  William F. Sauber

发明人： Gary Verdun ,  William F. Sauber

IPC分类号： G06F11/30

CPC分类号： G06F11/0745 ,  G06F1/26 ,  G06F11/0757 ,  G06F11/0793

摘要： A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.

公开(公告)号：US20120110381A1

公开(公告)日：2012-05-03

申请号：US12952464

申请日：2010-11-23

申请人： Gary Verdun ,  William F. Sauber

发明人： Gary Verdun ,  William F. Sauber

IPC分类号： G06F1/26 ,  G06F11/07

CPC分类号： G06F11/0745 ,  G06F1/26 ,  G06F11/0757 ,  G06F11/0793

摘要： A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.

公开(公告)号：US20120110380A1

公开(公告)日：2012-05-03

申请号：US12913029

申请日：2010-10-27

申请人： Gary Verdun ,  William F. Sauber

发明人： Gary Verdun ,  William F. Sauber

IPC分类号： G06F1/26 ,  G06F11/07

CPC分类号： G06F11/0757 ,  G06F1/26 ,  G06F11/0745

摘要： A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.

摘要翻译： 如果信息处理系统响应于正常掉电消息而断电，则强制断电信号通过光互连从I / O设备发送到信息处理系统。 100％占空比信号从I / O设备的光接口出现，并由信息处理系统的光接口检测到，该信号处理系统的光接口响应于强制功率发出强制信息处理系统断电的命令 下降信号。

公开(公告)号：US08373383B2

公开(公告)日：2013-02-12

申请号：US12578043

申请日：2009-10-13

申请人： Shree Dandekar ,  David Douglas ,  Gary Verdun ,  Gregory Dvorak

发明人： Shree Dandekar ,  David Douglas ,  Gary Verdun ,  Gregory Dvorak

IPC分类号： H02J7/00

CPC分类号： H02J7/0027 ,  H02J3/14 ,  H02J7/0021 ,  H02J7/041

摘要： A smart cart for automatically managing a plurality of information handling systems. The system provides a plurality of functions. For example, in certain embodiments, the system provides one or more of security authentication for distributing the notebooks, automatic asset tracking functionality; identification of notebook charge status; provides identification of asset information (e.g., an asset tag number, a serial number or a computer name); network access to push patch updates at night when units are not in use; and charging control to optimize system availability and prevent AC input circuit overload.

摘要翻译： 一种用于自动管理多个信息处理系统的智能车。 该系统提供多种功能。 例如，在某些实施例中，系统提供一种或多种用于分发笔记本电脑的安全认证，自动资产跟踪功能; 识别笔记本充电状态; 提供资产信息的识别（例如，资产标签号，序列号或计算机名称）; 网络访问在不使用单位的夜晚推送补丁更新; 充电控制优化系统可用性，防止交流输入电路过载。

公开(公告)号：US20070050549A1

公开(公告)日：2007-03-01

申请号：US11217023

申请日：2005-08-31

申请人： Gary Verdun

发明人： Gary Verdun

IPC分类号： G06F12/00

CPC分类号： G06F12/0888 ,  G06F2212/1028 ,  Y02D10/13

摘要： Systems and methods are disclosed for managing cacheability of data blocks to improve processor power management. Data can be intelligently moved between cache memory and non-cache memory based upon expected processing needs. Alternatively, the data can remain in the same memory space, and the memory designation can be intelligently managed from a cache memory to non-cache memory designation and/or from non-cache memory to cache memory designation depending upon the expected processing needs. In addition, both data movement and memory space re-designation can be utilized in conjunction. By intelligently managing the cacheability of the memory space holding the data blocks, processing efficiency and power management efficiency can be improved, particularly for bus master devices and related circuitry.

摘要翻译： 公开了用于管理数据块的高速缓存以提高处理器电源管理的系统和方法。 可以根据预期的处理需要，在高速缓冲存储器和非缓存存储器之间智能地移动数据。 或者，数据可以保持在相同的存储器空间中，并且可以根据期望的处理需要将存储器指定从高速缓冲存储器智能地管理到非缓存存储器指定和/或从非高速缓存存储器缓存存储器指定。 另外，可以结合使用数据移动和存储器空间重新指定。 通过智能地管理保持数据块的存储器空间的可缓存性，可以提高处理效率和电源管理效率，特别是对于总线主设备和相关电路。

公开(公告)号：US07049754B2

公开(公告)日：2006-05-23

申请号：US10885441

申请日：2004-07-06

申请人： Gary Verdun

发明人： Gary Verdun

IPC分类号： H05B37/00

CPC分类号： H05B41/2822

摘要： The impact of distributed capacitance on information handling system operations is reduced by introducing an impedance element in series with the ground of the source of the distributed capacitance for an overall reduction of capacitance. For instance, distributed capacitance is formed between a liquid crystal display illumination lamp and ground through a reflector disposed proximate the lamp and aligned so that an interior reflecting surface directs light toward imaging pixels. An insulating dielectric added to the outer surface of reflector and assembled to information handling system chassis ground with some surface area in common between the reflector and the system ground form a separate series capacitor between the lamp and ground. The insulation dielectric capacitance combines in series with the reflector capacitance to provide a resultant capacitance of less than the reflector capacitance. Reduced distributed capacitance of the lamp and wiring to ground reduces power loss and improves illumination brightness distribution across the lamp.

摘要翻译： 分布电容对信息处理系统操作的影响通过将阻抗元件与分布电容的源极接地串联以减小电容的整体而降低。 例如，通过设置在灯附近的反射器在液晶显示照明灯和地之间形成分布电容，并且对准，使得内部反射表面将光引向成像像素。 添加到反射器的外表面并组装到信息处理系统底盘接地的绝缘电介质，反射器和系统接地之间的一些共同的表面积在灯和地之间形成单独的串联电容器。 绝缘介质电容与反射器电容串联组合，以提供小于反射器电容的合成电容。 降低灯的分布电容和布线对地降低了功率损耗，并改善了整个灯的照明亮度分布。

公开(公告)号：US07017054B2

公开(公告)日：2006-03-21

申请号：US10188595

申请日：2002-07-02

申请人： Richard W. Schuckle ,  Gary Verdun

发明人： Richard W. Schuckle ,  Gary Verdun

IPC分类号： G06F1/32

CPC分类号： G06F1/32

摘要： A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory controller coupled to the processor bus. The memory controller performs snoop operations on the copy of the cache tag while the processor is placed in the lower power state. The processor exits the lower power state when an access to a modified cached line occurs.

摘要翻译： 一种用于减少耦合高速缓冲存储器和处理器的处理器总线上的窥探流量的方法和系统。 处理器在低功耗状态下无法进行窥探操作，以节省功耗。 在连接到处理器总线的存储器控​​制器中保持缓存标签的副本。 当处理器处于较低功率状态时，存储器控制器对高速缓存标签的副本执行窥探操作。 当发生对修改后的缓存行的访问时，处理器退出较低的电源状态。

公开(公告)号：US20050044448A1

公开(公告)日：2005-02-24

申请号：US10644427

申请日：2003-08-20

申请人： Gary Verdun

发明人： Gary Verdun

IPC分类号： G06F1/32 ,  G06F11/00 ,  G06F12/08

CPC分类号： G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0835 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

摘要： A system and method for managing power consumption and data integrity in a computer system is disclosed in which the a memory controller of the computer system records in a buffer the addresses of writes to system memory that occur during the period that the processor is in a low power state. When the processor exits the low power state, the processor invalidates in its internal cache those cache lines that correspond to the addresses recorded in the buffer.

摘要翻译： 公开了一种用于管理计算机系统中的功耗和数据完整性的系统和方法，其中计算机系统的存储器控​​制器在缓冲器中记录在处理器处于低电平期间发生的对系统存储器的写入地址 电源状态 当处理器退出低功率状态时，处理器在其内部高速缓存中使与缓冲器中记录的地址相对应的高速缓存行失效。

公开(公告)号：US07647515B2

公开(公告)日：2010-01-12

申请号：US11215260

申请日：2005-08-29

申请人： Gary Verdun

发明人： Gary Verdun

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3253 ,  G06F1/3228 ,  Y02D10/151

摘要： Power management of an information handling system PCI Express bus dynamically adjusts the inactivity time at the bus that is determined before initiation of a low power state by analyzing the transitions between low power and operating states over time. Dwell times of the bus in the low power state are compared with an inactivity goal to determine if the inactivity time should be adjusted up, such as when the bus enters the low power state too often, or should be adjusted down, such as when the bus enters the low power state too infrequently. In one embodiment, the dwell time is the time from entry into a low power state until initiation of the transition to an operating state and the inactivity goal is the time required for the bus to enter and exit the low power state.

摘要翻译： 信息处理系统的电源管理PCI Express总线通过分析低功耗和工作状态随时间的转换，动态地调整在启动低功耗状态之前确定的总线上的不活动时间。 将处于低功率状态的总线的停留时间与不活动目标进行比较，以确定是否应该调整不活动时间，例如当总线频繁进入低功率状态时，或者应当将其调低，例如当 总线很少进入低功率状态。 在一个实施例中，停留时间是从进入低功率状态直到转换到操作状态的开始的时间，并且不活动目标是总线进入和退出低功率状态所需的时间。