公开(公告)号：US20100005452A1

公开(公告)日：2010-01-07

申请号：US12217578

申请日：2008-07-07

申请人： Douglas M. Anson ,  Richard W. Schuckle

发明人： Douglas M. Anson ,  Richard W. Schuckle

IPC分类号： G06F9/44

CPC分类号： G06F9/44505

摘要： Methods and systems are described for factory configuration of existing customer settings so that existing customer settings can be easily configured or pre-configured on new information handling systems. A software module is run on a first information handling system that captures configuration information for an existing information handling system. One example for such configuration information is network configuration information associated with one or more existing wireless and/or wired networks on which a new information handling system will operate. Captured configuration information is transferred to a server information handling system associated with ordering of the new information handling system. The transferred configuration information is then used to configure the new information handling system.

摘要翻译： 描述了现有客户设置的出厂配置的方法和系统，以便可以在新的信息处理系统上轻松配置或预配置现有的客户设置。 软件模块在第一信息处理系统上运行，该系统捕获现有信息处理系统的配置信息。 这种配置信息的一个示例是与新信息处理系统将在其上操作的一个或多个现有无线和/或有线网络相关联的网络配置信息。 捕获的配置信息被传送到与新信息处理系统的排序相关联的服务器信息处理系统。 然后传输的配置信息用于配置新的信息处理系统。

公开(公告)号：US07644219B2

公开(公告)日：2010-01-05

申请号：US11171980

申请日：2005-06-30

申请人： Jimmy D. Pike ,  Richard W. Schuckle

发明人： Jimmy D. Pike ,  Richard W. Schuckle

IPC分类号： G06F13/36

CPC分类号： G06F9/4411

摘要： A system and method is disclosed for initializing PCI devices in a computer system or information handling system. Upon initialization of the system, each operating system instance of the system attempts to access a PCI bridge device. The first operating system to access the bridge device is granted ownership of the bridge device and the authority to initialize each PCI device coupled to the bridge device. The bridge device assigns each operating system to at least one context included in at least one of the PCI devices. After each of the PCI devices has been initialized, a configuration event is issued with respect to each operating system instance and each assigned PCI device, thereby causing each operating system to recognize each PCI device assigned to each respective operating system instance.

摘要翻译： 公开了一种用于在计算机系统或信息处理系统中初始化PCI设备的系统和方法。 在系统初始化时，系统的每个操作系统实例尝试访问PCI桥接器件。 获得桥接设备的第一个操作系统被授予桥接设备的所有权以及初始化耦合到桥接设备的每个PCI设备的权限。 桥接设备将每个操作系统分配给包括在至少一个PCI设备中的至少一个上下文。 在每个PCI设备已被初始化之后，针对每个操作系统实例和每个分配的PCI设备发出配置事件，从而使每个操作系统识别分配给每个相应操作系统实例的每个PCI设备。

公开(公告)号：US09319150B2

公开(公告)日：2016-04-19

申请号：US13662922

申请日：2012-10-29

申请人： Douglas J. Peeler ,  Richard W. Schuckle

发明人： Douglas J. Peeler ,  Richard W. Schuckle

IPC分类号： H04B15/00 ,  F16F15/00

CPC分类号： H04M1/72519 ,  F16F15/00 ,  G06F1/1626 ,  G06F3/016 ,  G10K2210/1291 ,  G10K2210/3032 ,  H04B15/00

摘要： An information handling system has a haptic generation module to generate haptic effects including haptic noise and a haptic noise reduction module. The haptic noise reduction module receives characteristics of sound representative of haptic noise generated by a haptic generation module of a device and entering an audio input module of the device, the characteristics including frequencies and timing. It also detects the generation of haptic effects, the generations occurring after the receiving characteristics. It also reduces the effects of haptic noise on digital data representing audio input to the device based upon the received characteristics of the sound. It may reduce the effects by subtracting amplitudes of audio waves representing the haptic noise from amplitudes of audio waves representing the audio input.

摘要翻译： 信息处理系统具有触觉生成模块，用于生成包括触觉噪声和触觉噪声降低模块的触觉效果。 触觉噪声降低模块接收代表由设备的触觉生成模块产生的触觉噪声的声音特性，并且输入该设备的音频输入模块，其特征包括频率和时序。 它还检测到触觉效应的产生，发生在接收特征之后。 它还基于接收的声音特性，减少了触觉噪声对表示音频输入到设备的数字数据的影响。 它可以通过从表示音频输入的音频波的幅度减去表示触觉噪声的音频波的幅度来减小效果。

公开(公告)号：US20140119569A1

公开(公告)日：2014-05-01

申请号：US13662922

申请日：2012-10-29

申请人： Douglas J. Peeler ,  Richard W. Schuckle

发明人： Douglas J. Peeler ,  Richard W. Schuckle

IPC分类号： H04B15/00

CPC分类号： H04M1/72519 ,  F16F15/00 ,  G06F1/1626 ,  G06F3/016 ,  G10K2210/1291 ,  G10K2210/3032 ,  H04B15/00

摘要： An information handling system has a haptic generation module to generate haptic effects including haptic noise and a haptic noise reduction module. The haptic noise reduction module receives characteristics of sound representative of haptic noise generated by a haptic generation module of a device and entering an audio input module of the device, the characteristics including frequencies and timing. It also detects the generation of haptic effects, the generations occurring after the receiving characteristics. It also reduces the effects of haptic noise on digital data representing audio input to the device based upon the received characteristics of the sound. It may reduce the effects by subtracting amplitudes of audio waves representing the haptic noise from amplitudes of audio waves representing the audio input.

摘要翻译： 信息处理系统具有触觉生成模块，用于生成包括触觉噪声和触觉噪声降低模块的触觉效果。 触觉噪声降低模块接收代表由设备的触觉生成模块产生的触觉噪声的声音特性，并且输入该设备的音频输入模块，其特征包括频率和时序。 它还检测到触觉效应的产生，发生在接收特征之后。 它还基于接收的声音特性，减少了触觉噪声对表示音频输入到设备的数字数据的影响。 它可以通过从表示音频输入的音频波的幅度减去表示触觉噪声的音频波的幅度来减小效果。

公开(公告)号：US20130024602A1

公开(公告)日：2013-01-24

申请号：US13185201

申请日：2011-07-18

申请人： William F. Sauber ,  Richard W. Schuckle

发明人： William F. Sauber ,  Richard W. Schuckle

IPC分类号： G06F12/00

CPC分类号： G06F3/0607 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/0676 ,  G06F12/0223

摘要： An information handling system (IHS) includes a processor and a single universal storage device with a system memory region and a mass storage region, wherein disk commands are executed by the processor as transfers between the system memory region and the mass storage region.

摘要翻译： 信息处理系统（IHS）包括具有系统存储区域和大容量存储区域的处理器和单个通用存储设备，其中，由系统存储器区域和大容量存储区域之间的传送由处理器执行盘命令。

公开(公告)号：US20100146267A1

公开(公告)日：2010-06-10

申请号：US12316189

申请日：2008-12-10

申请人： David Konetski ,  Richard W. Schuckle ,  Frank H. Molsberry

发明人： David Konetski ,  Richard W. Schuckle ,  Frank H. Molsberry

IPC分类号： H04L9/00

CPC分类号： G06F21/602 ,  G06F9/45533 ,  G06F12/14 ,  G06F21/53 ,  G06F21/60 ,  G06F21/70 ,  G06F21/86 ,  G06F21/87 ,  G06F2009/45587

摘要： Systems and methods for providing secure platform services using an information handling system, and which may be implemented to sequester or otherwise isolate sensitive cryptographic processes, as well as the keys used during such decryption and encryption processes. The systems and methods may be implemented as a set of secure services that are available to an operating system or to a Hypervisor executing on an information handling system, and the processing environment may be provided as a closed environment, thus preventing malicious code from infiltrating the processing environment. Dedicated and secure memory space may be employed to prevent key detection through memory scans.

摘要翻译： 用于使用信息处理系统提供安全平台服务的系统和方法，并且其可被实现为隔离或隔离敏感密码过程，以及在这样的解密和加密处理期间使用的密钥。 系统和方法可以被实现为可用于在信息处理系统上执行的操作系统或管理程序的一组安全服务，并且可以将处理环境提供为封闭环境，从而防止恶意代码渗透 处理环境。 可以采用专用和安全的存储器空间来防止通过存储器扫描的键检测。

公开(公告)号：US07017054B2

公开(公告)日：2006-03-21

申请号：US10188595

申请日：2002-07-02

申请人： Richard W. Schuckle ,  Gary Verdun

发明人： Richard W. Schuckle ,  Gary Verdun

IPC分类号： G06F1/32

CPC分类号： G06F1/32

摘要： A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory controller coupled to the processor bus. The memory controller performs snoop operations on the copy of the cache tag while the processor is placed in the lower power state. The processor exits the lower power state when an access to a modified cached line occurs.

摘要翻译： 一种用于减少耦合高速缓冲存储器和处理器的处理器总线上的窥探流量的方法和系统。 处理器在低功耗状态下无法进行窥探操作，以节省功耗。 在连接到处理器总线的存储器控​​制器中保持缓存标签的副本。 当处理器处于较低功率状态时，存储器控制器对高速缓存标签的副本执行窥探操作。 当发生对修改后的缓存行的访问时，处理器退出较低的电源状态。

公开(公告)号：US20150255070A1

公开(公告)日：2015-09-10

申请号：US14202190

申请日：2014-03-10

申请人： Richard W. Schuckle ,  Rocco Ancona ,  William Dale Todd Nix

发明人： Richard W. Schuckle ,  Rocco Ancona ,  William Dale Todd Nix

IPC分类号： G10L17/22 ,  G10L15/08

CPC分类号： G10L15/08 ,  G10L15/22 ,  G10L15/28 ,  G10L2015/088 ,  G10L2015/223

摘要： Systems and methods for managing wake-on-voice buffer quality based on system boot profiling. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include at least one logic circuit and at least one memory circuit coupled to the at least one logic circuit, the at least one memory including program instructions stored thereon that, upon execution by the at least one logic circuit, cause the IHS to: determine an expected time duration of a future wake event; receive a verbal command from a user, the verbal command configured to trigger the future wake event; capture the verbal command as an audio signal; adjust at least one of: a quality of the audio signal or a duration of the audio signal, where the adjustment is based, at least in part, upon the expected time duration; and store the adjusted audio signal in a fixed-size buffer.

摘要翻译： 基于系统引导分析管理唤醒语音缓冲区质量的系统和方法。 在说明性的非限制性实施例中，信息处理系统（IHS）可以包括至少一个逻辑电路和耦合到所述至少一个逻辑电路的至少一个存储器电路，所述至少一个存储器包括存储在其上的程序指令， 在由所述至少一个逻辑电路执行时，使所述IHS：确定未来唤醒事件的期望持续时间; 接收来自用户的口头命令，所述口头命令被配置为触发未来的唤醒事件; 捕获语音命令作为音频信号; 至少部分地基于所述预期持续时间来调整所述音频信号的质量或所述音频信号的持续时间中的至少一个; 并将经调整的音频信号存储在固定大小的缓冲器中。

公开(公告)号：US06420943B1

公开(公告)日：2002-07-16

申请号：US09478054

申请日：2000-01-05

申请人： Ricky S. Lewelling ,  Richard W. Schuckle

发明人： Ricky S. Lewelling ,  Richard W. Schuckle

IPC分类号： H01P508

CPC分类号： H01L23/522 ,  H01L21/76838 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A better impedance match between a signal transmitting component and a signal transmitting component circuit in a semiconductor circuit is achieved by controlling the parameters of the conducting path coupling the signal transmitting and receiving components. The parameters are controlled such that the portion of the conducting path coupled to the transmitting component has a characteristic impedance generally matching the output impedance of the transmitting component and the portion of the conducting path coupled to the signal receiving component has a characteristic impedance generally matching the input impedance of the signal receiving component. The impedance in portions of the conducting path can controlled by varying the geometric cross-section of the conducting path, the composition of the portion of the conducting path, and/or the amount or nature of the doping of the portion of the conducting path.

摘要翻译： 通过控制耦合信号发送和接收部件的传导路径的参数来实现半导体电路中的信号传输部件和信号传输部件电路之间更好的阻抗匹配。 参数被控制使得耦合到发射部件的导电路径的部分具有通常与发射部件的输出阻抗匹配的特性阻抗，并且耦合到信号接收部件的导电路径的部分具有通常匹配于 信号接收组件的输入阻抗。 导电路径部分的阻抗可以通过改变导电路径的几何横截面，导电路径部分的组成和/或导电路径部分的掺杂量或性质来控制。

公开(公告)号：US5915262A

公开(公告)日：1999-06-22

申请号：US681105

申请日：1996-07-22

申请人： K. Vincent Bridgers ,  Michael Drake ,  Richard W. Schuckle

发明人： K. Vincent Bridgers ,  Michael Drake ,  Richard W. Schuckle

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0802 ,  G06F12/0888 ,  G06F2212/206

摘要： A computer system including a processor, a main memory and a cache memory uses tagging of various regions of memory to define and select caching properties of transfers between the processor and memory via the cache. The main memory contains not only standard random access memory (RAM) and read-only memory (ROM) but also memory-mapped input/output (I/O) sources. Tagging of the memory regions configures the regions for association with a particular set of caching properties. For example, a memory-mapped video I/O buffer may be tagged with a MM.sub.-- IO.sub.-- VBUF tag designating the caching properties of write-back cacheability with weak read/write ordering. Low-level operating system software, such as the Hardware Abstraction Language (HAL) interface of the Windows NT.TM. operating system or device driver software, initialize the memory regions, the cache and make symbolic associations between the memory regions and the cache. The cache, operating as directed by the memory tags, allows read and write operations that are used for performing various types of multimedia or signal processing operations including decompression, drawing operations, compression, mixing, and the like, which are performed on a virtually-cached multimedia drawing surface. The data for performing the multimedia or signal processing operations are either already located on the I/O surface or read from another storage location local to the processor or from an external processor, which is also cached and tagged as a special cached region. The processor executes operations acting on the cached data. When all operations are completely executed by the processor, only the cached memory regions are flushed using a flush instruction such as CFLSH�MM.sub.-- IO.sub.-- VBUF!. The flush instruction directs the cache to write back and invalidate the regions having the designated tag, here MM.sub.-- IO.sub.-- VBUF.

摘要翻译： 包括处理器，主存储器和高速缓冲存储器的计算机系统使用各种存储器区域的标记来定义和选择经由高速缓存处理器和存储器之间的传送的高速缓存属性。 主存储器不仅包含标准随机存取存储器（RAM）和只读存储器（ROM），还包含存储器映射的输入/输出（I / O）源。 内存区域的标记将区域配置为与一组特定的缓存属性相关联。 例如，存储器映射的视频I / O缓冲器可以用指定具有弱读/写顺序的回写高速缓存的缓存特性的MM-IO-VBUF标签来标记。 低级操作系统软件，如Windows NT TM操作系统的硬件抽象语言（HAL）接口或设备驱动程序软件，初始化存储器区域，高速缓存并在存储器区域和高速缓存之间进行符号关联。 根据存储器标签的操作进行操作的高速缓存允许用于执行各种类型的多媒体或信号处理操作的读取和写入操作，包括解压缩，绘图操作，压缩，混合等， 缓存多媒体绘图面。 用于执行多媒体或信号处理操作的数据或者已经位于I / O表面上，或者从处理器本地的另一个存储位置读取或从外部处理器读取，外部处理器也被缓存并标记为特殊缓存区域。 处理器执行作用于缓存数据的操作。 当处理器完全执行所有操作时，仅使用诸如CFLSH [MM-IO-VBUF]的刷新指令来刷新缓存的存储器区域。 刷新指令指示高速缓存写入并使具有指定标签的区域无效，这里是MM-IO-VBUF。