公开(公告)号：US08126045B2

公开(公告)日：2012-02-28

申请号：US12201487

申请日：2008-08-29

申请人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

发明人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.

摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 通道门复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟门控的，用于在预充电时段期间从读出放大器的输出隔离后续电路。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选定信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。

公开(公告)号：US20100054324A1

公开(公告)日：2010-03-04

申请号：US12201487

申请日：2008-08-29

申请人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

发明人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.

摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 门控多路复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟选通的，用于在预充电期间将后续电路与读出放大器的输出隔离。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选择信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。

公开(公告)号：US07602869B2

公开(公告)日：2009-10-13

申请号：US11193868

申请日：2005-07-29

申请人： Azita Emami-Neyestanak ,  Mounir Meghelli ,  Benjamin D. Parker ,  Sergey V. Rylov ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Azita Emami-Neyestanak ,  Mounir Meghelli ,  Benjamin D. Parker ,  Sergey V. Rylov ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H04L7/00

CPC分类号： H04L7/0337

摘要： Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point. Further, for a next sampling cycle, the first clock may be used to sweep through phase positions with respect to the set phase position of the second clock corresponding to the sampling point in the first sampling cycle such that a next sampling point may be determined.

摘要翻译： 公开了时钟同步和数据恢复技术。 例如，用于同步用于恢复接收到的数据的时钟的技术包括以下步骤/操作。 将第一时钟（例如，数据时钟）设置为在接收到的数据中的给定单位间隔内的第一相位位置的第一采样周期。 第二时钟（例如，扫描时钟）相对于第一相位位置扫过其它相位位置，从而确定从接收到的数据中的给定单位间隔到另一个单位间隔的转变。 基于与第二时钟相关联的相位位置处的测量来确定采样点。 将第二时钟设置为对应于采样点的相位位置，使得可以在该采样点恢复数据。 此外，对于下一采样周期，可以使用第一时钟相对于与第一采样周期中的采样点对应的第二时钟的设置相位位置扫描相位位置，使得可以确定下一采样​​点。

公开(公告)号：US08552783B2

公开(公告)日：2013-10-08

申请号：US13158079

申请日：2011-06-10

申请人： Sergey V. Rylov

发明人： Sergey V. Rylov

IPC分类号： H03H11/26

CPC分类号： H03K5/131 ,  H03H11/265 ,  H03K2005/00065

摘要： A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line.

摘要翻译： 提供可编程延迟发生器和级联插值器。 可编程延迟发生器包括第一延迟线和第二延迟线，每个具有相同数量的相应多个级。 第一行的每一级包括相应的延迟缓冲器，并具有一个信号输入和一个信号输出。 第二行的每一级包括相应的选择元件，并且具有两个信号输入，一个选择输入用于选择两个信号输入之一和一个信号输出。 第一行和第二行并行配置，互连，并具有相同的信号传播方向。 由第二行的每一级提供的每个延迟步骤等于通过第一行的一级的延迟与通过第二行的一级的延迟之间的差。

公开(公告)号：US20090224811A1

公开(公告)日：2009-09-10

申请号：US12041913

申请日：2008-03-04

申请人： Hibourahima Camara ,  Sergey V. Rylov

发明人： Hibourahima Camara ,  Sergey V. Rylov

IPC分类号： H03H11/26

CPC分类号： G06F1/04

摘要： A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.

摘要翻译： 为时钟内插器提供调节缓冲器，时钟内插器控制时钟边沿的持续时间以实现高线性内插。 调理缓冲器包括具有固定或可变强度的第一缓冲器和第二缓冲器，其从一组相互延迟的时钟信号接收它们各自的输入，例如相互延迟为360 / N度的一组N个等距时钟相位 ，以形成对过程，温度和电压（PVT）变化不敏感的双抽头横向过滤器。 使用等距离的时钟相位使得这种横向滤波器的时间常数与时钟周期成比例，从而使其对时钟频率的变化不敏感。 结合缓冲器的自然带宽限制操作的这种横向滤波操作产生对PVT和时钟频率变化高度不敏感的有效时钟调节电路。

公开(公告)号：US07107301B2

公开(公告)日：2006-09-12

申请号：US10095206

申请日：2002-03-11

申请人： Sergey V. Rylov ,  Alexander V. Rylyakov ,  José A. Tierno

发明人： Sergey V. Rylov ,  Alexander V. Rylyakov ,  José A. Tierno

IPC分类号： G06F17/17 ,  G06F17/10

CPC分类号： H03H17/0223 ,  H03H17/0241 ,  H03H17/06 ,  H03K2005/00078

摘要： A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith. The processing circuitry is operatively configured to: (i) define a first subset of signal paths through the delay generation circuitry, the first subset including the zero delay signal path, and at least a second subset of signal paths through the delay generation circuitry, the second subset including one or more nonzero delay signal paths; (ii) remove an idle delay from all signal paths in the second subset, such that a shortest nonzero delay signal path in the second subset becomes a zero delay signal path; and (iii) incorporate the idle delay with the processing circuitry.

摘要翻译： 一种用于处理输入信号的数字信号处理装置包括延迟产生电路和处理电路。 延迟产生电路接收输入信号并且包括可操作地耦合在一起的多个延迟级，每个延迟级具有与之相关联的预定时间延迟。 延迟产生电路包括零延迟信号路径和与其相关联的至少一个非零延迟信号路径。 处理电路可操作地配置为：（i）通过延迟产生电路定义信号路径的第一子集，第一子集包括零延迟信号路径，以及通过延迟产生电路的信号路径的至少第二子集， 第二子集包括一个或多个非零延迟信号路径; （ii）从所述第二子集中的所有信号路径去除空闲延迟，使得所述第二子集中的最短非零延迟信号路径变为零延迟信号路径; 和（iii）将空闲延迟与处理电路相结合。

公开(公告)号：US5936458A

公开(公告)日：1999-08-10

申请号：US897475

申请日：1997-07-21

申请人： Sergey V. Rylov

发明人： Sergey V. Rylov

IPC分类号： H03K3/38

CPC分类号： H03K3/38 ,  Y10S505/855

摘要： Josephson transmission structures (JTSs) which include Josephson transmission lines (JTLs) with filter circuitry and flux release circuitry. Two or more of these JTSs may be interconnected to form a superconducting high-gain operational amplifier intended for general-purpose analog signal processing is disclosed. The active elements of the amplifier are non-hysteretic Josephson junctions configured as dc SQUIDs (used as flux-to voltage transducers and impedance transformers) and Josephson transmission lines (used as the main source of power gain). The amplifier has inverting and non-inverting voltage inputs, which can be fed from any low-resistance low-voltage sources, including dc SQUIDs. The output of the amplifier is in the form of a voltage which can drive typical transmission line impedances (e.g., 10-100 ohms). The variety of possible sources of input signals and the high gain of the amplifier enables wide range of applications including linear signal amplifiers, integrators, active filters and phase-locked oscillators.

摘要翻译： 约瑟夫逊传输结构（JTS），其包括具有滤波器电路和磁通释放电路的约瑟夫逊传输线（JTL）。 这些JTS中的两个或更多个可以互连以形成旨在用于通用模拟信号处理的超导高增益运算放大器。 放大器的有源元件是配置为直流SQUID（用作磁通至电压传感器和阻抗变压器）和约瑟夫逊传输线（用作功率增益的主要来源）的非滞后约瑟夫逊结。 放大器具有反相和非反相电压输入，可以从任何低电阻低电压源（包括直流SQUID）馈入。 放大器的输出是可以驱动典型传输线阻抗（例如，10-100欧姆）的电压的形式。 输入信号的各种可能的来源和放大器的高增益可以实现广泛的应用，包括线性信号放大器，积分器，有源滤波器和锁相振荡器。

公开(公告)号：US07659763B2

公开(公告)日：2010-02-09

申请号：US12041913

申请日：2008-03-04

申请人： Hibourahima Camara ,  Sergey V. Rylov

发明人： Hibourahima Camara ,  Sergey V. Rylov

IPC分类号： H03K3/013

CPC分类号： G06F1/04

摘要： A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.

摘要翻译： 为时钟内插器提供调节缓冲器，时钟内插器控制时钟边沿的持续时间以实现高线性内插。 调理缓冲器包括具有固定或可变强度的第一缓冲器和第二缓冲器，其从一组相互延迟的时钟信号接收它们各自的输入，例如相互延迟为360 / N度的一组N个等距时钟相位 ，以形成对过程，温度和电压（PVT）变化不敏感的双抽头横向过滤器。 使用等距离的时钟相位使得这种横向滤波器的时间常数与时钟周期成比例，从而使其对时钟频率的变化不敏感。 结合缓冲器的自然带宽限制操作的这种横向滤波操作产生对PVT和时钟频率变化高度不敏感的有效时钟调节电路。

公开(公告)号：US20080225990A1

公开(公告)日：2008-09-18

申请号：US12132022

申请日：2008-06-03

申请人： Troy James Beukema ,  Brian Allan Floyd ,  Scott Kevin Reynolds ,  Sergey V. Rylov

发明人： Troy James Beukema ,  Brian Allan Floyd ,  Scott Kevin Reynolds ,  Sergey V. Rylov

IPC分类号： H04L27/22

CPC分类号： H04L27/2273 ,  H04L1/206 ,  H04L27/0014 ,  H04L2027/0057

摘要： An apparatus and method to control signal phase in a radio device includes a phase rotator configured to control a phase of a local oscillator. A phase error determination module is configured to determine phase error information based on received in-phase (I) and quadrature (Q) (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.

摘要翻译： 控制无线电设备中的信号相位的装置和方法包括配置成控制本地振荡器的相位的相位旋转器。 相位误差确定模块被配置为基于接收到的同相（I）和正交（Q）（IQ）信号值来确定相位误差信息。 相位校正模块被配置为从所接收的IQ信号值导出校正信号，并将校正信号施加到本地振荡器的路径中的相位旋转器。

公开(公告)号：US06903579B2

公开(公告)日：2005-06-07

申请号：US10607468

申请日：2003-06-26

申请人： Sergey V. Rylov ,  Alexander V. Rylyakov

发明人： Sergey V. Rylov ,  Alexander V. Rylyakov

IPC分类号： H03K19/173 ,  H03K19/20

CPC分类号： H03K19/1738

摘要： Multiple-input CML gates with a stack height of one are provided by using a composite device wherein input signals are propagated to the output through two or more stages of CML-like primitives connected in succession. A universal three-input CML gate (a 2:1 multiplexor) is provided by using a two-stage pipeline, and can be used to build other logic devices, such as AND, OR, and XOR functions, or a latch. The pipelined CML gates with a stack height of one provide a substantially improved voltage-speed trade-off under low-voltage conditions.

摘要翻译： 通过使用复合器件提供堆叠高度为1的多输入CML门，其中输入信号通过连续连接的两个或多个类似CML的原语传播到输出。 通过使用两级管线提供通用三输入CML门（2：1多路复用器），并可用于构建其他逻辑器件，如AND，OR和XOR函数或锁存器。 堆叠高度为1的流水线CML栅极在低电压条件下提供了显着改善的电压速度折衷。