公开(公告)号：US08126045B2

公开(公告)日：2012-02-28

申请号：US12201487

申请日：2008-08-29

申请人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

发明人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.

摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 通道门复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟门控的，用于在预充电时段期间从读出放大器的输出隔离后续电路。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选定信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。

公开(公告)号：US20100054324A1

公开(公告)日：2010-03-04

申请号：US12201487

申请日：2008-08-29

申请人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

发明人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.

摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 门控多路复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟选通的，用于在预充电期间将后续电路与读出放大器的输出隔离。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选择信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。

公开(公告)号：US07602869B2

公开(公告)日：2009-10-13

申请号：US11193868

申请日：2005-07-29

申请人： Azita Emami-Neyestanak ,  Mounir Meghelli ,  Benjamin D. Parker ,  Sergey V. Rylov ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Azita Emami-Neyestanak ,  Mounir Meghelli ,  Benjamin D. Parker ,  Sergey V. Rylov ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H04L7/00

CPC分类号： H04L7/0337

摘要： Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point. Further, for a next sampling cycle, the first clock may be used to sweep through phase positions with respect to the set phase position of the second clock corresponding to the sampling point in the first sampling cycle such that a next sampling point may be determined.

摘要翻译： 公开了时钟同步和数据恢复技术。 例如，用于同步用于恢复接收到的数据的时钟的技术包括以下步骤/操作。 将第一时钟（例如，数据时钟）设置为在接收到的数据中的给定单位间隔内的第一相位位置的第一采样周期。 第二时钟（例如，扫描时钟）相对于第一相位位置扫过其它相位位置，从而确定从接收到的数据中的给定单位间隔到另一个单位间隔的转变。 基于与第二时钟相关联的相位位置处的测量来确定采样点。 将第二时钟设置为对应于采样点的相位位置，使得可以在该采样点恢复数据。 此外，对于下一采样周期，可以使用第一时钟相对于与第一采样周期中的采样点对应的第二时钟的设置相位位置扫描相位位置，使得可以确定下一采样​​点。

公开(公告)号：US07961778B2

公开(公告)日：2011-06-14

申请号：US12177231

申请日：2008-07-22

申请人： James F. Buckwalter ,  Daniel J. Friedman ,  Mounir Meghelli

发明人： James F. Buckwalter ,  Daniel J. Friedman ,  Mounir Meghelli

IPC分类号： H04B17/00 ,  H04Q1/20

CPC分类号： H04L25/03343 ,  H03K5/135 ,  H03M9/00 ,  H04J3/047 ,  H04J3/0685 ,  H04L7/0037 ,  H04L25/03885

摘要： In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.

摘要翻译： 在高速串行链路的上下文中，使用相位预失真执行的数据相关抖动补偿技术。 广泛考虑的是将预加重的概念扩展超出ISI的常规幅度补偿，由此引入用于补偿依赖于数据的抖动（DDJ）的相位预加重。 可以通过利用数据序列与时序偏差之间的关系来解决DDJ。 相位预加重提高了信号完整性，在发射机中几乎没有额外的功耗，没有串扰。

公开(公告)号：US20080137790A1

公开(公告)日：2008-06-12

申请号：US11608962

申请日：2006-12-11

申请人： Hayden C. Cranford ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

发明人： Hayden C. Cranford ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

IPC分类号： H04L7/00

CPC分类号： H04L7/0004 ,  H04L7/0334

摘要： A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the DRR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

摘要翻译： 公开了一种双模式时钟和数据恢复（CDR）系统。 快速锁定，过采样CDR采集模块可以开始该过程，以在启动数据采集条件下快速创建数据采集时钟信号。 当从输入数据流中提取至少一些数据时，DRR系统可以指示这种稳定性，并切换到接受来自低功率CDR维护模块的控制。 低功率CDR维护模块可以微调并保持数据采集信号的定时。 如果CDR维护模块控制下的数据锁定质量下降到足够的程度，高功率CDR采集模块可以重新启用并重新从低功率模块重新进行控制，直到锁定质量再次足够 要使用的低功耗模块。

公开(公告)号：US07721134B2

公开(公告)日：2010-05-18

申请号：US11566576

申请日：2006-12-04

申请人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

发明人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

IPC分类号： H04L25/00 ,  H03D3/24

CPC分类号： G01R31/3171 ,  B82Y25/00 ,  G01R33/093

摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.

摘要翻译： 提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。 接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘采样，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对 到数据采样时钟。 接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。 该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。 边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。

公开(公告)号：US20070025483A1

公开(公告)日：2007-02-01

申请号：US11193868

申请日：2005-07-29

申请人： Azita Emami-Neyestanak ,  Mounir Meghelli ,  Benjamin Parker ,  Sergey Rylov ,  Alexander Rylyakov ,  Jose Tierno

发明人： Azita Emami-Neyestanak ,  Mounir Meghelli ,  Benjamin Parker ,  Sergey Rylov ,  Alexander Rylyakov ,  Jose Tierno

IPC分类号： H04L7/00

CPC分类号： H04L7/0337

摘要： Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point. Further, for a next sampling cycle, the first clock may be used to sweep through phase positions with respect to the set phase position of the second clock corresponding to the sampling point in the first sampling cycle such that a next sampling point may be determined.

摘要翻译： 公开了时钟同步和数据恢复技术。 例如，用于同步用于恢复接收到的数据的时钟的技术包括以下步骤/操作。 将第一时钟（例如，数据时钟）设置为在接收到的数据中的给定单位间隔内的第一相位位置的第一采样周期。 第二时钟（例如，扫频时钟）相对于第一相位位置被扫过其它相位位置，从而确定在接收数据中从给定单位间隔到另一个单位间隔的转变。 基于与第二时钟相关联的相位位置处的测量来确定采样点。 将第二时钟设置为对应于采样点的相位位置，使得可以在该采样点恢复数据。 此外，对于下一采样周期，可以使用第一时钟相对于与第一采样周期中的采样点对应的第二时钟的设置相位位置扫描相位位置，使得可以确定下一采样​​点。

公开(公告)号：US07916820B2

公开(公告)日：2011-03-29

申请号：US11608962

申请日：2006-12-11

申请人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

发明人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

IPC分类号： H04L7/00

CPC分类号： H04L7/0004 ,  H04L7/0334

摘要： A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

摘要翻译： 公开了一种双模式时钟和数据恢复（CDR）系统。 快速锁定，过采样CDR采集模块可以开始该过程，以在启动数据采集条件下快速创建数据采集时钟信号。 当从输入数据流中至少提取一些数据时，CDR系统可以指示这种稳定性，并切换到接受来自低功率CDR维护模块的控制。 低功率CDR维护模块可以微调并保持数据采集信号的定时。 如果CDR维护模块控制下的数据锁定质量下降到足够的程度，高功率CDR采集模块可以重新启用并重新从低功率模块重新进行控制，直到锁定质量再次足够 要使用的低功耗模块。

公开(公告)号：US20080148088A1

公开(公告)日：2008-06-19

申请号：US11930345

申请日：2007-10-31

申请人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  Timothy Clyde Buchholtz ,  Daniel Mark Dreps ,  Charles Porter Geer ,  Mounir Meghelli ,  Sergey Vladimirovich Rylov ,  David W. Siljenberg ,  Dana Marie Woeste

发明人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  Timothy Clyde Buchholtz ,  Daniel Mark Dreps ,  Charles Porter Geer ,  Mounir Meghelli ,  Sergey Vladimirovich Rylov ,  David W. Siljenberg ,  Dana Marie Woeste

IPC分类号： G06F11/00

CPC分类号： G06F13/4204 ,  Y02D10/14 ,  Y02D10/151

摘要： A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

摘要翻译： 用于高速计算机处理器系统的设计结构包括用于图形处理器的高速接口。 在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

公开(公告)号：US20080055036A1

公开(公告)日：2008-03-06

申请号：US11512014

申请日：2006-08-29

申请人： Keith A. Jenkins ,  Mounir Meghelli

发明人： Keith A. Jenkins ,  Mounir Meghelli

IPC分类号： H01F5/00

CPC分类号： H01F17/0013 ,  H01F21/12 ,  H01F41/045 ,  H01F2021/125 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/165 ,  H01L2924/00

摘要： Techniques are disclosed for fabricating tunable electrical components in integrated circuits. For example, a method of tuning a value of an electrical component, such as a planar inductor, includes the steps of placing a conductive layer in proximity of the electrical component, and adjusting an amount of material that constitutes the conductive layer such that the value of the electrical component is tuned to a particular value. The adjustment step may be performed so as to select a frequency band with which the inductor is associated or to correct a manufacturing deviation in a frequency with which the inductor is associated.

摘要翻译： 公开了用于在集成电路中制造可调电气部件的技术。 例如，调整诸如平面电感器的电气部件的值的方法包括以下步骤：将导电层放置在电气部件附近，以及调整构成导电层的材料的量，使得值 的电气元件被调谐到特定的值。 可以执行调整步骤以便选择与电感器相关联的频带或者校正与电感器相关联的频率中的制造偏差。