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1.发明授权
公开(公告)号：US4608664A
公开(公告)日：1986-08-26
申请号：US469180
申请日：1983-02-23
CPC分类号： G06F17/25
摘要： Text and graphics are justified along one physical dimension to a predetermined line of justification. A plurality of physical parameters are employed in the justification, each of the parameters is assigned a compression and an expansion adjustment ratio. Such ratios define the maximum adjustment range of each of the parameters. A priority of adjustment is assigned to each of the parameters such that one parameter being adjusted and capable of meeting justification needs is adjusted to the exclusion of all other possible parameter adjustments. In vertical justification of a plurality of columns, text distribution precedes the vertical adjustment. For such vertical justification, the priority of adjustment is based upon natural text/graphics breaks; top priority is use of lead outs, second is skips, third is spaces and last is textual adjustments. Justification is preferably proportional, i.e., the ratios are adjusted when the maximum permitted adjustment is not required for justification. For horizontal justification, similar ratio selections apply.
摘要翻译： 文本和图形沿着一个物理维度被合理化为预定的对齐线。 在对齐中使用多个物理参数，每个参数被分配压缩和扩展调整比。 这些比率定义了每个参数的最大调整范围。 调整优先级被分配给每个参数，使得被调整并且能够满足调整需求的一个参数被调整为排除所有其他可能的参数调整。 在多个列的垂直对齐中，文本分布先于垂直调整。 对于这种垂直的理由，调整的优先次序是基于自然文本/图形中断; 优先使用铅笔，二是跳过，第三是空格，最后是文字调整。 理由最好是成比例的，即当调整不需要最大允许调整时调整比率。 对于水平对齐，适用比例选择。
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2.发明授权
公开(公告)号：US4575813A
公开(公告)日：1986-03-11
申请号：US469181
申请日：1983-02-23
IPC分类号： G06F3/12 , B41B27/00 , G03F1/90 , G06F17/21 , G06F17/24 , G06F17/25 , G06T11/60 , G09G5/00 , G09G5/32 , B41B17/00 , B41J11/44
CPC分类号： G06F17/25 , G06F17/245
摘要： Text and graphics are recursively (includes iteratively) distributed among a set of balanceable columns capable of receiving text and graphics. The recursive distributions are at successively varying columnar depths (all columns in each recursion have a common target depth), upon completing each recursion, the difference between the resulting shortest and longest column depths is measured and compared with a standard. If the standard is met, the distribution is made final, otherwise subsequent recursions up to a predetermined number of recursions are employed. If the standard is not met, then after the predetermined number of recursions, the distribution yielding the least differential is selected as the final distribution. Vertical justification of the columns follows.
摘要翻译： 文本和图形递归（包括迭代）分布在一组能够接收文本和图形的平衡列之间。 递归分布是连续变化的柱状深度（每个递归中的所有列都具有公共目标深度），在完成每个递归后，测量所得到的最短和最长列深度之间的差异并与标准进行比较。 如果满足标准，则分配是最终的，否则采用直到预定数量的递归的后续递归。 如果不满足标准，则在预定次数的递归之后，选择产生最小差分的分布作为最终分布。 列的垂直对齐方式如下。
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3.发明授权
公开(公告)号：US4539653A
公开(公告)日：1985-09-03
申请号：US484032
申请日：1983-04-11
CPC分类号： G06T11/60
摘要： Machine-implemented text/graphics formatting is based upon a logical page area on a presentation-receiving medium, such as a CRT face, sheet of paper and the like. Named text and graphics receiving areas are selectively assignable to the logical pages of a document being formatted for visual presentation and are addressable and formattable independent of other formatting in any logical page. The named areas are machine defined such that one area can have portions thereof automatically assigned to and presented with any arbitrary number of logical pages. Such areas are managed in a text formatting machine to facilitate formatting headers based upon text contained in a succession of logical pages that are outside the named area. A first class of such named areas is placed upon the page when formatting to the page is ended, while a second class of such named areas is placed on the page in response to a command. The placement of the second class on a page can result in starting formatting new pages. Bleed tabs, annotations, and other typographic niceties are machine formattable using such named areas.
摘要翻译： 机器实现的文本/图形格式化基于呈现接收介质上的逻辑页面区域，诸如CRT面，纸张等。 命名的文本和图形接收区域可选择性地分配给被格式化用于可视呈现的文档的逻辑页面，并且是可寻址的和格式化的，独立于任何逻辑页面中的其他格式化。 命名区域是机器定义的，使得一个区域可以具有自动分配给任何数量的逻辑页面并呈现任何数量的逻辑页面的部分。 这样的区域在文本格式化机器中进行管理以便于基于在命名区域之外的一系列逻辑页面中包含的文本来格式化标题。 当页面的格式化结束时，这种命名区域的第一类被放置在页面上，而响应命令将第二类这样的命名区域放置在页面上。 在页面上放置第二个类可能会导致格式化新页面。 出版的标签，注释和其他印刷细节是使用这种命名区域的机器格式。
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4.发明申请Method and circuit for low-power detection of solder-joint network failures in digital electronic packages 审中-公开数字电子封装焊点网络故障低功耗检测方法与电路公开(公告)号：US20080144243A1
公开(公告)日：2008-06-19
申请号：US11803562
申请日：2007-05-14
CPC分类号： G01R31/048
摘要： A low power circuit and method for detects in-situ failures or precursors to failures in solder-joint networks on actual operational devices and packages in the field. An amplifying detector such as provided by a common-gate transistor sources current to the network to generate a signal voltage and a reference voltage that is sensitive to the low voltage applied to the other side of the network. Generation of this self-adjusting reference voltage makes the detection circuit insensitive to the network low-voltage. Additional power savings and performance gains can be provided with the addition of a differential amplifier to set a fixed bias point and a level shifter to cancel noise. The detected failure or precursor of a selected monitor solder-joint network(s) is an indicator of the integrity of other operational solder-joint networks in the package, on the PWB or between PWBs.
摘要翻译： 一种低功率电路和方法，用于在现场的实际操作设备和封装上检测原位故障或焊接网络故障的前兆。 诸如由公共栅极晶体管提供的放大检测器将电流源流到网络以产生对施加到网络的另一侧的低电压敏感的信号电压和参考电压。 产生这种自调节参考电压使得检测电路对网络的低电压不敏感。 通过添加差分放大器来设置固定偏置点和电平移位器来消除噪声，可以提供额外的功率节省和性能增益。 检测到的所选监测器焊点网络的故障或前体是PWB或PWB之间的封装中其他操作焊点网络的完整性的指示。
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公开(公告)号：US20120232814A1
公开(公告)日：2012-09-13
申请号：US13407341
申请日：2012-02-28
IPC分类号： G06F19/00
CPC分类号： G01R31/40
摘要： The present invention provides a frequency-sampling circuit and method for characterizing a health condition of a test unit attached to a power supply. The frequency-sampling circuit is connected externally to the test unit. The circuit comprises an inductor and a capacitor connected in series at an output. When switched, the circuit resonates with an AC loop current to produce a damped-frequency response at the output. Frequency measurements of this response are processed to generate SoH or RUL estimates for the test unit. The voltages applied within the frequency-sampling circuit are limited, which in turn limits the AC loop current to avoid loading the power supply. Incorporating the inductance and capacitance with in the frequency-sampling circuit allows the circuit to be configured for different classes of test units having a wide range of characteristic impedances.
摘要翻译： 本发明提供了一种用于表征附接到电源的测试单元的健康状况的频率采样电路和方法。 频率采样电路从外部连接到测试单元。 该电路包括在输出端串联连接的电感器和电容器。 当切换时，电路与交流回路电流谐振，以在输出端产生阻尼 - 频率响应。 处理此响应的频率测量结果，以生成测试单元的SoH或RUL估计值。 施加在频率采样电路内的电压受到限制，从而限制了交流回路电流，以避免加载电源。 将频率采样电路中的电感和电容结合在一起可使电路配置为具有宽范围特性阻抗的不同类别的测试单元。
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6.发明申请Prognostic Health Monitoring in Switch-Mode Power Supplies with Voltage Regulation 失效具有电压调节功能的开关电源中的预测健康监测公开(公告)号：US20080015795A1
公开(公告)日：2008-01-17
申请号：US11778835
申请日：2007-07-17
IPC分类号： G06F19/00
CPC分类号： G05B23/0256 , G05B23/0283 , G05F1/40
摘要： The system includes a current injection device in electrical communication with the switch mode power supply. The current injection device is positioned to alter the initial, non-zero load current when activated. A prognostic control is in communication with the current injection device, controlling activation of the current injection device. A frequency detector is positioned to receive an output signal from the switch mode power supply and is able to count cycles in a sinusoidal wave within the output signal. An output device is in communication with the frequency detector. The output device outputs a result of the dounted cycles, which are indicative of damage to an a remaining useful life of the switch mode power supply.
摘要翻译： 该系统包括与开关模式电源电气通信的电流注入装置。 当前的注射装置被定位成在被激活时改变初始的非零负载电流。 预测控制与当前注射装置通信，控制电流注射装置的激活。 频率检测器被定位成接收来自开关模式电源的输出信号，并且能够对输出信号内的正弦波进行计数周期。 输出设备与频率检测器通信。 输出装置输出被安装的循环的结果，这表示对开关模式电源的剩余使用寿命的损坏。
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7.发明申请CIRCUIT FOR THE DETECTION OF SOLDER-JOINT FAILURES IN A DIGITAL ELECTRONIC PACKAGE 失效用于检测数字电子包装中的焊接失败的电路公开(公告)号：US20090160457A1
公开(公告)日：2009-06-25
申请号：US12360046
申请日：2009-01-26
IPC分类号： G01R31/02
CPC分类号： G01R31/048 , G01R31/2884 , G01R31/312
摘要： The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.
摘要翻译： 数字电子封装（例如具有内部连接的输入/输出缓冲器的微控制器）的焊接完整性通过通过一个或多个焊点网络施加时变电压来对电荷存储部件进行充电来评估。 每个网络包括在封装中的管芯上的I / O缓冲器和焊接接头，通常在封装内部以及封装与板之间的一个或多个这样的连接。 用于对部件充电的时间常数与焊点网络的电阻成比例，因此电荷存储部件两端的电压是测量焊点网络的完整性。
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8.发明授权Method and circuit for the detection of solder-joint failures in a digital electronic package 失效用于检测数字电子封装中焊点故障的方法和电路公开(公告)号：US07501832B2
公开(公告)日：2009-03-10
申请号：US11325076
申请日：2006-01-04
IPC分类号： G01R31/02
CPC分类号： G01R31/048 , G01R31/2884 , G01R31/312
摘要： The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.
摘要翻译： 数字电子封装（例如具有内部连接的输入/输出缓冲器的微控制器）的焊接完整性通过通过一个或多个焊点网络施加时变电压来对电荷存储部件进行充电来评估。 每个网络包括在封装中的管芯上的I / O缓冲器和焊接接头，通常在封装内部以及封装与板之间的一个或多个这样的连接。 用于对部件充电的时间常数与焊点网络的电阻成比例，因此电荷存储部件两端的电压是测量焊点网络的完整性。
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9.发明授权Method and resistive bridge circuit for the detection of solder-joint failures in a digital electronic package 失效用于检测数字电子封装中焊点故障的方法和电阻桥式电路公开(公告)号：US07196294B2
公开(公告)日：2007-03-27
申请号：US11350446
申请日：2006-02-09
IPC分类号： H05B1/02
CPC分类号： G01R31/048 , B23K1/0016 , B23K2101/40 , G01R31/2884 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： A solder-joint detection circuit uses a resistive bridge and a differential detector to detect faults in the solder-joint network both inside and outside the digital electronic package during operation. The resistive bridge is preferably coupled to a high supply voltage used to power the package. Resistors R1 and R2 are connected in series at a first junction between the high and low supply voltages and a resistor R3 is coupled to the high supply voltage and connected in series with the resistance of the solder-network at a second junction. The network is held at a low voltage on the die. The detector compares the sensitivity and detection voltages and outputs a Pass/Fail signal for the solder-joint network.
摘要翻译： 焊接检测电路使用电阻桥和差分检测器来检测数字电子封装内部和外部的焊点网络中的故障。 电阻桥优选地耦合到用于为封装供电的高电源电压。 电阻器R 1和R 2在高电源电压和低电源电压之间的第一连接处串联连接，并且电阻器R 3耦合到高电源电压并且在第二连接处与焊料网络的电阻串联连接。 网络在模具上保持低电压。 检测器比较灵敏度和检测电压，并输出焊点网络的通过/失败信号。
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