公开(公告)号：US20080273373A1

公开(公告)日：2008-11-06

申请号：US12146554

申请日：2008-06-26

申请人： George M. Braceras ,  Wilfried E. A. Haensch ,  Joseph A. Iadanza

发明人： George M. Braceras ,  Wilfried E. A. Haensch ,  Joseph A. Iadanza

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.

摘要翻译： 一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点 在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗， 其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。

公开(公告)号：US07408800B1

公开(公告)日：2008-08-05

申请号：US11743686

申请日：2007-05-03

申请人： George M. Braceras ,  Wilfried E. A. Haensch ,  Joseph A. Iadanza

发明人： George M. Braceras ,  Wilfried E. A. Haensch ,  Joseph A. Iadanza

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.

摘要翻译： 一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点 在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗， 其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。

公开(公告)号：US07729159B2

公开(公告)日：2010-06-01

申请号：US12146554

申请日：2008-06-26

申请人： George M. Braceras ,  Wilfried E. A. Haensch ,  Joseph A. Iadanza

发明人： George M. Braceras ,  Wilfried E. A. Haensch ,  Joseph A. Iadanza

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.

摘要翻译： 一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点 在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗， 其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。

公开(公告)号：US20080273366A1

公开(公告)日：2008-11-06

申请号：US11851408

申请日：2007-09-07

申请人： George M. Braceras ,  Wilfried E.A. Haensch ,  Joseph A. Iadanza

发明人： George M. Braceras ,  Wilfried E.A. Haensch ,  Joseph A. Iadanza

IPC分类号： G11C5/06

CPC分类号： G11C11/412 ,  G11C11/413

摘要： A design structure embodied in a machine readable medium used in a design process includes a static random access memory (SRAM) device having a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括具有一对交叉耦合的互补金属氧化物半导体（CMOS）逆变器的静态随机存取存储器（SRAM）器件，其被配置为用于数据位的存储单元 配置为在所述设备的读取操作期间将所述存储单元的互补内部节点耦合到对应的位线对的第一对传输门; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗， 其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。

公开(公告)号：US20130223161A1

公开(公告)日：2013-08-29

申请号：US13403252

申请日：2012-02-23

申请人： Igor Arsovski ,  George M. Braceras ,  Harold Pilo

发明人： Igor Arsovski ,  George M. Braceras ,  Harold Pilo

IPC分类号： G11C7/10

CPC分类号： G11C5/147 ,  G11C11/417

摘要： An integrated circuit structure comprises a static random access memory (SRAM) structure and a logic circuit. A power supply is operatively connected to the SRAM structure, and provides a first voltage to the SRAM structure. A voltage limiter is operatively connected to the power supply. The voltage limiter comprises a switching device operatively connected to the power supply. The switching device receives the first voltage and a second voltage supplied to structures external to the SRAM structure. A resistive element is operatively connected to the switching device. The switching device connects the resistive element to the power supply. The resistive element is selected to enable an output from the switching device to the logic circuit when a difference between the first voltage and the second voltage is greater than a voltage threshold value of the switching device.

摘要翻译： 集成电路结构包括静态随机存取存储器（SRAM）结构和逻辑电路。 电源可操作地连接到SRAM结构，并且向SRAM结构提供第一电压。 电压限制器可操作地连接到电源。 电压限制器包括可操作地连接到电源的开关装置。 开关器件接收提供给SRAM结构外部结构的第一电压和第二电压。 电阻元件可操作地连接到开关装置。 开关装置将电阻元件连接到电源。 电阻元件被选择为当第一电压和第二电压之间的差大于开关器件的电压阈值时，使能从开关器件到逻辑电路的输出。

公开(公告)号：US07180320B2

公开(公告)日：2007-02-20

申请号：US10995791

申请日：2004-11-23

申请人： George M. Braceras ,  Harold Pilo

发明人： George M. Braceras ,  Harold Pilo

IPC分类号： G01R31/26

CPC分类号： G01R31/3004

摘要： BUR920020148US13 A method of tuning an integrated circuit on an integrated circuit chip including: performing a drain current at saturation measurement of one or more test field effect transistors on the integrated circuit chip; selectively programming fuses of a bank of fuses on the integrated circuit chip based on the drain current at saturation measurement; and tuning an output of the integrated circuit based on a pattern of blown and un-blown fuses in the bank of fuses.

摘要翻译： 一种对集成电路芯片上的集成电路进行调谐的方法，包括：在集成电路芯片上的一个或多个测试场效应晶体管的饱和测量时执行漏极电流; 基于饱和度测量时的漏极电流有选择地对集成电路芯片上的熔丝组进行熔丝; 并根据保险丝库中的熔断和未熔断保险丝的模式调整集成电路的输出。

公开(公告)号：US06999547B2

公开(公告)日：2006-02-14

申请号：US10065840

申请日：2002-11-25

申请人： George M. Braceras ,  Harold Pilo

发明人： George M. Braceras ,  Harold Pilo

IPC分类号： H04L7/033

CPC分类号： H03L7/00

摘要： A Delay-Lock-Loop circuit and a method for producing a phase shift comprises a phase generator producing a first and second clock signal having a first and second rising edge, respectively, wherein a timing difference between the first and second rising edges is equal to a desired cycle time; a delay circuit operable to receive the first clock signal and to produce a delayed clock signal; and a latch element connected to the delay circuit, and operable to check whether the delayed clock signal is delayed by an amount equal to the desired cycle time; a plurality of serially connected binary-weighted inverters connected to the latch element, which are operable to adjust the delay of the delayed clock signal to be equal to the desired cycle time; and a phase-shifted delay circuit connected to the delay circuit, and operable to produce multiple degrees of phase shift of the delayed clock signal.

摘要翻译： 延迟锁定环电路和产生相移的方法包括相位发生器，分别产生具有第一和第二上升沿的第一和第二时钟信号，其中第一和第二上升沿之间的定时差等于 期望的周期时间; 延迟电路，其可操作以接收所述第一时钟信号并产生延迟的时钟信号; 以及锁存元件，连接到所述延迟电路，并且可操作以检查延迟的时钟信号是否被延迟等于期望周​​期时间的量; 连接到所述锁存元件的多个串行连接的二进制加权反相器，其可操作以将延迟的时钟信号的延迟调整为等于期望的周期时间; 以及连接到所述延迟电路的相移延迟电路，并且可操作以产生延迟的时钟信号的多个相移。

公开(公告)号：US06392949B2

公开(公告)日：2002-05-21

申请号：US09761460

申请日：2001-01-16

申请人： George M. Braceras ,  Harold Pilo

发明人： George M. Braceras ,  Harold Pilo

IPC分类号： G11C300

CPC分类号： G11C11/417 ,  G11C7/1039 ,  G11C11/418

摘要： A high performance memory array architecture is provided to minimize the delays within each array. The architecture of the array equalizes the access time to all memory elements by optimizing the positioning of the subarrays with respect to buffering and rebuffering elements used in the array which cause delays.

公开(公告)号：US20120075919A1

公开(公告)日：2012-03-29

申请号：US12892191

申请日：2010-09-28

申请人： Igor Arsovski ,  George M. Braceras ,  Kevin W. Gorman ,  Robert M. Houle ,  Harold Pilo

发明人： Igor Arsovski ,  George M. Braceras ,  Kevin W. Gorman ,  Robert M. Houle ,  Harold Pilo

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C8/08

摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.

摘要翻译： 在制造的SRAM中设置字线上电压的方法。 在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。 然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。 提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

公开(公告)号：US07894291B2

公开(公告)日：2011-02-22

申请号：US11162847

申请日：2005-09-26

申请人： George M. Braceras ,  John A. Fifield ,  Harold Pilo

发明人： George M. Braceras ,  John A. Fifield ,  Harold Pilo

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/147

摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.

摘要翻译： 提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。 存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值 消费。 电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。 存储器的存储单元阵列可操作以存储数据。 在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。 这在待机模式期间允许数据保存在存储器中。 在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。 在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。