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1.发明授权Implementing at-speed Wafer Final Test (WFT) with complete chip coverage 失效以完整的芯片覆盖率实施高速晶圆终端测试（WFT）公开(公告)号：US07852103B2
公开(公告)日：2010-12-14
申请号：US12429263
申请日：2009-04-24
申请人： Gerald Keith Bartley , Darryl John Becker , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson , Dennis Martin Rickert
发明人： Gerald Keith Bartley , Darryl John Becker , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson , Dennis Martin Rickert
CPC分类号： H01L22/32 , G01R31/318511 , H01L2924/0002 , H01L2924/00
摘要： A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.
摘要翻译： 提供了一种方法，装置和计算机程序产品，用于实现具有包括高速片外接收器和驱动器输入/输出（I / O）电路在内的总集成电路芯片覆盖的速度晶片最终测试（WFT）。 集成电路（IC）芯片包括片外控制崩溃芯片连接（C4）节点和片外接收器的驱动器和接收器以及连接到各个片外C4节点的驱动器输入/输出（I / O）电路 。 通过硅通道（TSV）被添加到驱动器和接收器以及相应的片外C4节点的连接到IC芯片的背面。 在连接TSV的IC芯片背面添加金属线，并在驱动器和接收器之间创建用于I / O电路的高速WFT测试的连接路径。
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2.发明申请公开(公告)号：US20100271046A1
公开(公告)日：2010-10-28
申请号：US12429263
申请日：2009-04-24
申请人： Gerald Keith Bartley , Darryl John Becker , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson , Dennis Martin Rickert
发明人： Gerald Keith Bartley , Darryl John Becker , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson , Dennis Martin Rickert
IPC分类号： H01H31/02
CPC分类号： H01L22/32 , G01R31/318511 , H01L2924/0002 , H01L2924/00
摘要： A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.
摘要翻译： 提供了一种方法，装置和计算机程序产品，用于实现具有包括高速片外接收器和驱动器输入/输出（I / O）电路在内的总集成电路芯片覆盖的速度晶片最终测试（WFT）。 集成电路（IC）芯片包括片外控制崩溃芯片连接（C4）节点和片外接收器的驱动器和接收器以及连接到各个片外C4节点的驱动器输入/输出（I / O）电路 。 通过硅通道（TSV）被添加到驱动器和接收器以及相应的片外C4节点的连接到IC芯片的背面。 在连接TSV的IC芯片背面添加金属线，并在驱动器和接收器之间创建用于I / O电路的高速WFT测试的连接路径。
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公开(公告)号：US08296707B2
公开(公告)日：2012-10-23
申请号：US12948165
申请日：2010-11-17
CPC分类号： G06F17/5072 , G06F2217/72
摘要： A method, system and computer program product are provided for implementing spare latch placement quality (SLPQ) determination in a floor plan design of an integrated circuit chip. A spare latch placement quality (SLPQ) metric data function is defined and compared to a spare latch placement input with a series of calculations performed. The spare latch placement quality (SLPQ) determination is made based upon the compared SLPQ metric data function and the spare latch placement input. Then associated reports including textual and visual reports are generated responsive to the SLPQ determination. In addition, a new spare latch placement can be constructed with an algorithm responsive to the SLPQ determination.
摘要翻译： 提供了一种方法，系统和计算机程序产品，用于在集成电路芯片的平面图设计中实现备用锁存放置质量（SLPQ）确定。 定义了备用锁定位置质量（SLPQ）度量数据功能，并与执行一系列计算的备用锁存器放置输入进行比较。 基于比较的SLPQ度量数据功能和备用锁存器位置输入来进行备用锁存器布局质量（SLPQ）确定。 然后响应于SLPQ确定生成包括文本和视觉报告的关联报告。 此外，可以使用响应于SLPQ确定的算法来构造新的备用锁存器放置。
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4.发明授权Method and dual interlocked storage cell latch for implementing enhanced testability 失效方法和双互锁存储单元锁存器，用于实现增强的可测试性公开(公告)号：US07661047B2
公开(公告)日：2010-02-09
申请号：US11870015
申请日：2007-10-10
IPC分类号： G01R31/28 , H03K3/00 , H03K3/289 , H03K19/003
CPC分类号： G01R31/318533 , G11C29/32 , G11C2029/3202
摘要： A method and Dual Interlocked Storage Cell (DICE) latch for implementing enhanced testability, and a design structure on which the subject DICE latch circuit resides are provided. DICE latch includes an L1 latch and an L2 latch are coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode.
摘要翻译： 一种用于实现增强的可测试性的方法和双联锁存储单元（DICE）锁存器，以及提供主题DICE锁存电路所在的设计结构。 DICE锁存器包括L1锁存器，L2锁存器耦合到L1锁存器。 每个L1锁存器和每个L2锁存器包括冗余锁存结构。 冗余L2锁存器提供单独的输出。 DICE锁存器包括冗余测试锁存器使能（RTLE）输入。 每个L1锁存器和每个L2锁存器包括通过RTLE输入控制的冗余锁存结构中的路径选择器控制，其在测试模式期间提供扫描路径中的每个冗余锁存结构。
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5.发明申请Method and Apparatus for Implementing Logic Security Feature for Disabling Integrated Circuit Test Ports Ability to Scanout Data 有权实现逻辑安全特性的方法和装置，用于禁用集成电路测试端口能够扫描数据公开(公告)号：US20090172819A1
公开(公告)日：2009-07-02
申请号：US11964093
申请日：2007-12-26
IPC分类号： G06F21/22
CPC分类号： G01R31/31719
摘要： A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.
摘要翻译： 提供一种用于实现集成电路安全特征的方法和装置，以选择性地禁用集成电路芯片上的可测试性特征。 测试禁止逻辑电路接收测试使能信号并响应于测试模式的测试使能信号设置，建立测试模式并禁用ASIC信号。 响应于未设置的测试使能信号，ASIC信号使能功能模式，并且集成电路芯片上的可测试功能被禁用。 当启用功能模式时，测试禁止逻辑电路可防止在集成电路芯片通电时建立测试模式。
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6.发明授权Implementing logic security feature for disabling integrated circuit test ports ability to scanout data 有权实现逻辑安全功能，禁用集成电路测试端口扫描数据的能力公开(公告)号：US08166357B2
公开(公告)日：2012-04-24
申请号：US11964093
申请日：2007-12-26
IPC分类号： G01R31/28
CPC分类号： G01R31/31719
摘要： A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.
摘要翻译： 提供一种用于实现集成电路安全特征的方法和装置，以选择性地禁用集成电路芯片上的可测试性特征。 测试禁止逻辑电路接收测试使能信号并响应于测试模式的测试使能信号设置，建立测试模式并禁用ASIC信号。 响应于未设置的测试使能信号，ASIC信号使能功能模式，并且集成电路芯片上的可测试功能被禁用。 当启用功能模式时，测试禁止逻辑电路可防止在集成电路芯片通电时建立测试模式。
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7.发明授权Method and dual interlocked storage cell latch for implementing enhanced testability 失效方法和双互锁存储单元锁存器，用于实现增强的可测试性公开(公告)号：US07661046B2
公开(公告)日：2010-02-09
申请号：US11682081
申请日：2007-03-05
IPC分类号： G01R31/28 , H03K3/00 , H03K3/289 , H03K19/003
CPC分类号： G01R31/318541
摘要： A method and a Dual Interlocked Storage Cell (DICE) latch implementing enhanced testability includes an L1 latch and an L2 latch coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode.
摘要翻译： 实现增强可测性的方法和双联锁存储单元（DICE）锁存器包括耦合到L1锁存器的L1锁存器和L2锁存器。 每个L1锁存器和每个L2锁存器包括冗余锁存结构。 冗余L2锁存器提供单独的输出。 DICE锁存器包括冗余测试锁存器使能（RTLE）输入。 每个L1锁存器和每个L2锁存器包括通过RTLE输入控制的冗余锁存结构中的路径选择器控制，其在测试模式期间提供扫描路径中的每个冗余锁存结构。
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公开(公告)号：US20120124541A1
公开(公告)日：2012-05-17
申请号：US12948165
申请日：2010-11-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/72
摘要： A method, system and computer program product are provided for implementing spare latch placement quality (SLPQ) determination in a floor plan design of an integrated circuit chip. A spare latch placement quality (SLPQ) metric data function is defined and compared to a spare latch placement input with a series of calculations performed. The spare latch placement quality (SLPQ) determination is made based upon the compared SLPQ metric data function and the spare latch placement input. Then associated reports including textual and visual reports are generated responsive to the SLPQ determination. In addition, a new spare latch placement can be constructed with an algorithm responsive to the SLPQ determination.
摘要翻译： 提供了一种方法，系统和计算机程序产品，用于在集成电路芯片的平面图设计中实现备用锁存放置质量（SLPQ）确定。 定义了备用锁定位置质量（SLPQ）度量数据功能，并与执行一系列计算的备用锁存器放置输入进行比较。 基于比较的SLPQ度量数据功能和备用锁存器位置输入来进行备用锁存器布局质量（SLPQ）确定。 然后响应于SLPQ确定生成包括文本和视觉报告的关联报告。 此外，可以使用响应于SLPQ确定的算法来构造新的备用锁存器放置。
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9.发明申请Method and Dual Interlocked Storage Cell Latch for Implementing Enhanced Testability 失效方法和双联锁存储单元锁存器，用于实现增强的可测试性公开(公告)号：US20080222469A1
公开(公告)日：2008-09-11
申请号：US11870015
申请日：2007-10-10
IPC分类号： G01R31/28
CPC分类号： G01R31/318533 , G11C29/32 , G11C2029/3202
摘要： A method and Dual Interlocked Storage Cell (DICE) latch for implementing enhanced testability, and a design structure on which the subject DICE latch circuit resides are provided. DICE latch includes an L1 latch and an L2 latch are coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode.
摘要翻译： 一种用于实现增强的可测试性的方法和双联锁存储单元（DICE）锁存器，以及提供主题DICE锁存电路所在的设计结构。 DICE锁存器包括L1锁存器，L2锁存器耦合到L1锁存器。 每个L1锁存器和每个L2锁存器包括冗余锁存结构。 冗余L2锁存器提供单独的输出。 DICE锁存器包括冗余测试锁存器使能（RTLE）输入。 每个L1锁存器和每个L2锁存器包括通过RTLE输入控制的冗余锁存结构中的路径选择器控制，其在测试模式期间提供扫描路径中的每个冗余锁存结构。
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10.发明申请Method and Dual Interlocked Storage Cell Latch for Implementing Enhanced Testability 失效方法和双联锁存储单元锁存器，用于实现增强的可测试性公开(公告)号：US20080222468A1
公开(公告)日：2008-09-11
申请号：US11682081
申请日：2007-03-05
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： A method and a Dual Interlocked Storage Cell (DICE) latch implementing enhanced testability includes an L1 latch and an L2 latch coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode.
摘要翻译： 实现增强可测性的方法和双联锁存储单元（DICE）锁存器包括耦合到L1锁存器的L1锁存器和L2锁存器。 每个L1锁存器和每个L2锁存器包括冗余锁存结构。 冗余L2锁存器提供单独的输出。 DICE锁存器包括冗余测试锁存器使能（RTLE）输入。 每个L1锁存器和每个L2锁存器包括通过RTLE输入控制的冗余锁存结构中的路径选择器控制，其在测试模式期间提供扫描路径中的每个冗余锁存结构。
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