公开(公告)号：US07945883B2

公开(公告)日：2011-05-17

申请号：US12172300

申请日：2008-07-14

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/78

摘要： A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.

摘要翻译： 提供了一种用于通过电子封装设计中的网格平面实现垂直耦合噪声控制的方法，装置和计算机程序产品。 接收电子封装物理设计数据。 识别电子封装物理设计数据中垂直耦合噪声的实例。 所确定的垂直耦合噪声的实例被量化。 然后修改电子封装物理设计数据，以限制垂直耦合噪声。

公开(公告)号：US07852103B2

公开(公告)日：2010-12-14

申请号：US12429263

申请日：2009-04-24

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson ,  Dennis Martin Rickert

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson ,  Dennis Martin Rickert

IPC分类号： G01R31/02 ,  G01R31/26 ,  H01L23/58

CPC分类号： H01L22/32 ,  G01R31/318511 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.

摘要翻译： 提供了一种方法，装置和计算机程序产品，用于实现具有包括高速片外接收器和驱动器输入/输出（I / O）电路在内的总集成电路芯片覆盖的速度晶片最终测试（WFT）。 集成电路（IC）芯片包括片外控制崩溃芯片连接（C4）节点和片外接收器的驱动器和接收器以及连接到各个片外C4节点的驱动器输入/输出（I / O）电路 。 通过硅通道（TSV）被添加到驱动器和接收器以及相应的片外C4节点的连接到IC芯片的背面。 在连接TSV的IC芯片背面添加金属线，并在驱动器和接收器之间创建用于I / O电路的高速WFT测试的连接路径。

公开(公告)号：US07673093B2

公开(公告)日：2010-03-02

申请号：US11459974

申请日：2006-07-26

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

IPC分类号： G06F12/06

CPC分类号： G06F13/4243 ,  G06F13/4256

摘要： A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.

摘要翻译： 具有具有存储器控制器和存储器的存储器系统的计算机系统。 存储器控制器耦合到处理器和存储器。 存储器包括一个或多个存储器芯片的菊花链。 地址/命令字通过存储器芯片的菊花链链接并由存储器芯片的菊花链中的一个存储器芯片来处理。 作为地址/命令字的一部分发送要写入存储器芯片的数据，或者在输出数据总线链上传送。 从存储芯片读取的数据在传入数据总线链上传输。 存储器芯片的菊花链可以包括多个载体上的存储器芯片，或者存储器芯片的菊花链都可以连接到单个载体。

公开(公告)号：US07660940B2

公开(公告)日：2010-02-09

申请号：US11459983

申请日：2006-07-26

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

IPC分类号： G06F12/06

CPC分类号： G06F13/1684 ,  G11C7/10

摘要： A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.

摘要翻译： 一种在存储器芯片的菊花链中具有至少一个自定时存储器芯片的载体。 第一载体具有连接到第一载体的存储芯片的菊链的至少一部分。 第一载波上的地址/命令总线输入将地址/命令字携带到存储器芯片的菊花链中的第一存储器芯片。 如果第一存储器芯片确定地址/命令字不指向第一存储器芯片，则第一存储器芯片使用点对点将地址/命令字重新驱动到存储器芯片的菊花链中的第二存储器芯片 地址/命令总线链路。 如果第一个载波上没有更多的存储器芯片，则地址/命令字被重新驱动到地址/命令总线非承载连接器。 存储器芯片上的阵列具有动态确定阵列可访问速度的访问时间。

公开(公告)号：US20090300411A1

公开(公告)日：2009-12-03

申请号：US12132120

申请日：2008-06-03

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  William Paul Hovis ,  Mark Owen Maxson

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  William Paul Hovis ,  Mark Owen Maxson

IPC分类号： G06F11/14

CPC分类号： G06F11/1666 ,  G06F11/2092

摘要： A method and apparatus implement redundant memory access using multiple controllers for a memory system, and a design structure on which the subject circuit resides are provided. A first memory controller uses a first memory and a second memory controller uses the second memory as its respective primary address space, for storage and fetches. The second memory controller is also connected to the first memory. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. When one of the first memory controller or the second memory controller fails, then the other memory controller is notified. The other memory controller takes control of the memory for the failed controller, using the direct connection to that memory, and maintains coherence of both the first memory and second memory.

摘要翻译： 一种使用存储系统的多个控制器实现冗余存储器访问的方法和装置，以及设置有主题电路所在的设计结构。 第一存储器控制器使用第一存储器，并且第二存储器控制器使用第二存储器作为其相应的主地址空间，用于存储和提取。 第二存储器控制器也连接到第一存储器。 第一存储器控制器也连接到第二存储器。 例如，第一存储器控制器和第二存储器控制器通过处理器通信总线连接在一起。 当第一个存储器控制器或第二个存储器控制器中的一个发生故障时，则通知另一个存储器控制器。 另一个存储器控制器使用与该存储器的直接连接来控制故障控制器的存储器，并保持第一存储器和第二存储器的相干性。

公开(公告)号：US07620763B2

公开(公告)日：2009-11-17

申请号：US11459943

申请日：2006-07-26

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

IPC分类号： G06F13/40 ,  G06F13/28

CPC分类号： G06F13/4243

摘要： A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to be written into an array on the memory chip; the read portion is dedicated to driving data that has been read from the array on the memory chip. The apportionment is programmable. Apportionment can be specified by programming signal pins on the memory chip, connecting the signal pins to appropriate logical values. The apportionment can alternatively be specified by scanning apportionment information into the memory chip at bring up time. The apportionment and also alternatively be specified by receiving apportionment information in an address/command word.

摘要翻译： 一种具有数据总线的存储器芯片，具有多个位。 比特数在读取部分和写入部分之间分配。 写入部分专用于接收要写入存储器芯片中的阵列的数据; 读取部分专用于驱动已经从存储器芯片上的阵列读取的数据。 分配是可编程的。 分配可以通过编程存储器芯片上的信号引脚指定，将信号引脚连接到适当的逻辑值。 可以通过在启动时间内将分配信息扫描到存储器芯片来指定分配。 分配也可以通过在地址/命令字中接收分配信息来指定。

公开(公告)号：US07617350B2

公开(公告)日：2009-11-10

申请号：US11459969

申请日：2006-07-26

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

IPC分类号： G06F12/06 ,  G06F13/42

CPC分类号： G06F13/4243

摘要： A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to a memory chip on a second carrier.

摘要翻译： 具有存储芯片的菊花链中的至少一个存储器芯片的载体。 第一载体具有连接到第一载体的存储芯片的整个菊花链的至少一部分。 第一载波上的地址/命令总线输入将地址/命令字携带到存储器芯片的菊花链中的第一存储器芯片。 如果第一存储器芯片确定地址/命令字不指向第一存储器芯片，则第一存储器芯片使用点对点将地址/命令字重新驱动到存储器芯片的菊花链中的第二存储器芯片 地址/命令总线链路。 如果第一载波上没有更多的存储器芯片，地址/命令字被重新驱动到第二个载体上的存储器芯片。

公开(公告)号：US07345901B2

公开(公告)日：2008-03-18

申请号：US11459968

申请日：2006-07-26

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

IPC分类号： G11C5/06 ,  G11C5/02 ,  G06F12/00

CPC分类号： G11C5/00 ,  G11C7/10

摘要： A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on each memory chip is determined by a self time block on each memory chip.

摘要翻译： 一种具有存储器系统的计算机系统，所述存储器系统具有存储器控制器和存储器。 存储器包括一个或多个自定时存储器芯片的菊花链。 地址/命令字通过存储器芯片的菊花链链接并由存储器芯片的菊花链中的一个存储器芯片来处理。 作为地址/命令字的一部分发送要写入存储器芯片的数据，或者在输出数据总线链上传送。 从存储芯片读取的数据在传入数据总线链上传输。 每个存储器芯片上的访问定时由每个存储器芯片上的自身时间块确定。

公开(公告)号：US07342816B2

公开(公告)日：2008-03-11

申请号：US11459994

申请日：2006-07-26

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

IPC分类号： G11C5/06 ,  G11C7/10

CPC分类号： G11C29/32 ,  G11C5/04 ,  G11C8/12 ,  G11C29/26 ,  G11C2029/3202

摘要： A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip respondent to the address/command word. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. Read data is read from the array or is received from a second data bus port for subsequent re-driving on the first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port.

摘要翻译： 适用于存储芯片的菊花链的存储芯片。 存储器芯片在第一输入端接收地址/命令字，确定地址命令字是否被引导到存储器芯片; 如果是这样，则存储器芯片访问对地址/命令字应答的存储器芯片上的阵列。 如果不是，则存储器芯片在第一输出上重新驱动地址/命令字。 作为地址/命令字的一部分或从第一数据总线端口接收写入数据。 从阵列中读取数据或从第二数据总线端口接收数据，以便随后在第一数据总线端口重新驱动。 接收总线时钟并用于接收和发送关于第一输入，第一输出，第一数据总线端口和第二数据总线端口的信息。

公开(公告)号：US20080028126A1

公开(公告)日：2008-01-31

申请号：US11459959

申请日：2006-07-26

申请人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

发明人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

IPC分类号： G06F12/00 ,  G06F13/40

CPC分类号： G06F13/1684

摘要： A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.

摘要翻译： 一种具有存储器控制器和存储器芯片的菊花链的存储器系统。 存储器控制器通过地址/命令总线链耦合到存储器芯片的菊花链中的存储器芯片。 存储器控制器通过具有多个数据总线位的数据总线链耦合到存储器芯片的菊花链中的存储器芯片。 数据总线链具有专用于从存储器控制器向存储器芯片发送写数据的数据总线位的第一部分。 数据总线链具有专用于从存储器芯片向存储器控制器发送读取数据的数据总线位的第二部分。 数据总线位在第一部分和第二部分之间的分配是可编程的。 编程通过引脚连接，值的扫描，或者通过与存储器控制器耦合的处理器的请求来完成。