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    Implementing at-speed Wafer Final Test (WFT) with complete chip coverage
    6.
    发明授权
    Implementing at-speed Wafer Final Test (WFT) with complete chip coverage 失效
    以完整的芯片覆盖率实施高速晶圆终端测试（WFT）

    公开(公告)号：US07852103B2

    公开(公告)日：2010-12-14

    申请号：US12429263

    申请日：2009-04-24

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson ,  Dennis Martin Rickert

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson ,  Dennis Martin Rickert

    IPC分类号： G01R31/02 ,  G01R31/26 ,  H01L23/58

    CPC分类号： H01L22/32 ,  G01R31/318511 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.

    摘要翻译： 提供了一种方法，装置和计算机程序产品，用于实现具有包括高速片外接收器和驱动器输入/输出（I / O）电路在内的总集成电路芯片覆盖的速度晶片最终测试（WFT）。 集成电路（IC）芯片包括片外控制崩溃芯片连接（C4）节点和片外接收器的驱动器和接收器以及连接到各个片外C4节点的驱动器输入/输出（I / O）电路 。 通过硅通道（TSV）被添加到驱动器和接收器以及相应的片外C4节点的连接到IC芯片的背面。 在连接TSV的IC芯片背面添加金属线，并在驱动器和接收器之间创建用于I / O电路的高速WFT测试的连接路径。

    Computer system having daisy chained memory chips
    7.
    发明授权
    Computer system having daisy chained memory chips 失效
    具有菊花链式存储芯片的计算机系统

    公开(公告)号：US07673093B2

    公开(公告)日：2010-03-02

    申请号：US11459974

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F12/06

    CPC分类号： G06F13/4243 ,  G06F13/4256

    摘要： A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.

    摘要翻译： 具有具有存储器控制器和存储器的存储器系统的计算机系统。 存储器控制器耦合到处理器和存储器。 存储器包括一个或多个存储器芯片的菊花链。 地址/命令字通过存储器芯片的菊花链链接并由存储器芯片的菊花链中的一个存储器芯片来处理。 作为地址/命令字的一部分发送要写入存储器芯片的数据，或者在输出数据总线链上传送。 从存储芯片读取的数据在传入数据总线链上传输。 存储器芯片的菊花链可以包括多个载体上的存储器芯片，或者存储器芯片的菊花链都可以连接到单个载体。

    Carrier having daisy chain of self timed memory chips
    8.
    发明授权
    Carrier having daisy chain of self timed memory chips 失效
    载体具有自定时存储芯片的菊花链

    公开(公告)号：US07660940B2

    公开(公告)日：2010-02-09

    申请号：US11459983

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F12/06

    CPC分类号： G06F13/1684 ,  G11C7/10

    摘要： A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.

    摘要翻译： 一种在存储器芯片的菊花链中具有至少一个自定时存储器芯片的载体。 第一载体具有连接到第一载体的存储芯片的菊链的至少一部分。 第一载波上的地址/命令总线输入将地址/命令字携带到存储器芯片的菊花链中的第一存储器芯片。 如果第一存储器芯片确定地址/命令字不指向第一存储器芯片，则第一存储器芯片使用点对点将地址/命令字重新驱动到存储器芯片的菊花链中的第二存储器芯片 地址/命令总线链路。 如果第一个载波上没有更多的存储器芯片，则地址/命令字被重新驱动到地址/命令总线非承载连接器。 存储器芯片上的阵列具有动态确定阵列可访问速度的访问时间。

    Memory chip having an apportionable data bus
    9.
    发明授权
    Memory chip having an apportionable data bus 有权
    具有可分配数据总线的存储芯片

    公开(公告)号：US07620763B2

    公开(公告)日：2009-11-17

    申请号：US11459943

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F13/40 ,  G06F13/28

    CPC分类号： G06F13/4243

    摘要： A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to be written into an array on the memory chip; the read portion is dedicated to driving data that has been read from the array on the memory chip. The apportionment is programmable. Apportionment can be specified by programming signal pins on the memory chip, connecting the signal pins to appropriate logical values. The apportionment can alternatively be specified by scanning apportionment information into the memory chip at bring up time. The apportionment and also alternatively be specified by receiving apportionment information in an address/command word.

    摘要翻译： 一种具有数据总线的存储器芯片，具有多个位。 比特数在读取部分和写入部分之间分配。 写入部分专用于接收要写入存储器芯片中的阵列的数据; 读取部分专用于驱动已经从存储器芯片上的阵列读取的数据。 分配是可编程的。 分配可以通过编程存储器芯片上的信号引脚指定，将信号引脚连接到适当的逻辑值。 可以通过在启动时间内将分配信息扫描到存储器芯片来指定分配。 分配也可以通过在地址/命令字中接收分配信息来指定。

    Carrier having daisy chained memory chips
    10.
    发明授权
    Carrier having daisy chained memory chips 失效
    载体具有菊花链式存储芯片

    公开(公告)号：US07617350B2

    公开(公告)日：2009-11-10

    申请号：US11459969

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F12/06 ,  G06F13/42

    CPC分类号： G06F13/4243

    摘要： A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to a memory chip on a second carrier.

    摘要翻译： 具有存储芯片的菊花链中的至少一个存储器芯片的载体。 第一载体具有连接到第一载体的存储芯片的整个菊花链的至少一部分。 第一载波上的地址/命令总线输入将地址/命令字携带到存储器芯片的菊花链中的第一存储器芯片。 如果第一存储器芯片确定地址/命令字不指向第一存储器芯片，则第一存储器芯片使用点对点将地址/命令字重新驱动到存储器芯片的菊花链中的第二存储器芯片 地址/命令总线链路。 如果第一载波上没有更多的存储器芯片，地址/命令字被重新驱动到第二个载体上的存储器芯片。