公开(公告)号：US06282116B1

公开(公告)日：2001-08-28

申请号：US09603337

申请日：2000-06-26

申请人： Gerhard Kunkel ,  Shahid Butt ,  Carl J Radens

发明人： Gerhard Kunkel ,  Shahid Butt ,  Carl J Radens

IPC分类号： G11C1124

CPC分类号： H01L27/10882 ,  G11C11/4097 ,  H01L27/10841

摘要： A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

摘要翻译： 动态随机存取存储器形成在芯片阵列中的硅芯片中，四个单元中的每一个在单个活动区域中。 每个有源区域在两个十字准线的四端处具有垂直沟槽十字形。 两个交叉点相交的有源区域的中心区域用作簇的四个晶体管的公共基极区域。 基极区域的顶部用作四个晶体管的公共漏极，并且每个晶体管沿其相关联的垂直沟槽的壁具有提供其存储电容器的单独沟道。 每个集群包括一个公共位线和四个单独的字线触点。

公开(公告)号：US06743670B2

公开(公告)日：2004-06-01

申请号：US10382894

申请日：2003-03-06

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J Radens ,  Joseph F. Shepard, Jr.

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J Radens ,  Joseph F. Shepard, Jr.

IPC分类号： H01L218242

CPC分类号： H01L29/945 ,  H01L21/28194 ,  H01L21/31604 ,  H01L21/3162 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/517 ,  H01L29/66181

摘要： A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.

摘要翻译： 用于改进的DRAM（动态随机存取存储器）电介质结构的方法和结构，由此为用作栅极电介质的支撑器件以及电容器电介质实现新的高k材料。 该方法形成用于电容器器件的深的隔离沟槽区域和用于支持器件的浅隔离沟槽区域。 该方法还形成两个不同的绝缘体层，其中具有均匀的高k介电常数的一个绝缘体层用于深沟槽区域和支撑区域。 另一个绝缘体层用于浅沟槽区域之间的阵列区域。

公开(公告)号：US07190042B2

公开(公告)日：2007-03-13

申请号：US10722353

申请日：2003-11-25

申请人： Ramachandra Divakaruni ,  Jack A Mandelman ,  Carl J Radens

发明人： Ramachandra Divakaruni ,  Jack A Mandelman ,  Carl J Radens

IPC分类号： H01L21/336 ,  H01L29/00

CPC分类号： H01L27/10867 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/0207 ,  H01L27/10864

摘要： A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically align to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.

摘要翻译： 通过蚀刻衬底中的多个垂直深沟槽并用氧化阻挡层涂覆沟槽，形成用于存储单元阵列的自对准浅沟槽隔离区。 氧化阻挡层凹陷在沟槽的部分中以暴露沟槽中的衬底的部分。 衬底的暴露部分通过氧化合并成热氧化物区域，以形成隔离衬底材料的相邻部分的自对准浅沟槽隔离结构。 合并的氧化物区域是自对准的，因为它们在合并在一起时自动对准深沟槽的边缘，以在IC制造期间限定存储单元阵列内的隔离区域的位置。 瞬时自对准浅沟槽隔离结构避免了需要隔离掩模以在单个衬底上的相邻有效区域行内分离或隔离多个沟槽。

公开(公告)号：US07892932B2

公开(公告)日：2011-02-22

申请号：US12054699

申请日：2008-03-25

申请人： Kangguo Cheng ,  Carl J Radens

发明人： Kangguo Cheng ,  Carl J Radens

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.

摘要翻译： 具有施加拉伸和/或压缩应变的半导体器件及其制造半导体器件的方法和设计结构以增强通道应变。 该方法包括为NFET和PFET形成栅极结构，并使用相同的沉积和蚀刻工艺在NFET和PFET的栅极结构上形成侧壁。 该方法还包括在NFET和PFET的源极和漏极区域中提供应力材料。