公开(公告)号：US06566219B2

公开(公告)日：2003-05-20

申请号：US09957937

申请日：2001-09-21

申请人： Gerhard Kunkel ,  Shahid Butt ,  Ramachandra Divakaruni ,  Armin M. Reith ,  Munir D. Naeem

发明人： Gerhard Kunkel ,  Shahid Butt ,  Ramachandra Divakaruni ,  Armin M. Reith ,  Munir D. Naeem

IPC分类号： H01L21475

CPC分类号： H01L27/10864 ,  H01L27/1087 ,  H01L27/10891

摘要： A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) is formed over a semiconductor region (e.g., a silicon substrate). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

摘要翻译： 形成沟槽的方法可用于制造动态随机存取存储器（DRAM）单元。 在一个方面，在半导体区域（例如，硅衬底）上形成第一材料（例如，多晶硅）的第一层。 图案化第一层以去除第一材料的部分。 然后可以沉积第二材料（例如，氧化物）以填充去除第一材料的部分。 在去除第一材料的第一层的剩余部分之后，可以在半导体区域中蚀刻沟槽。 沟槽将基本上对准第二材料。

公开(公告)号：US06404019B1

公开(公告)日：2002-06-11

申请号：US09676870

申请日：2000-09-29

申请人： Armin M. Reith ,  Tina Leidinger ,  Gunther Lehmann

发明人： Armin M. Reith ,  Tina Leidinger ,  Gunther Lehmann

IPC分类号： H01L2994

CPC分类号： G11C7/065 ,  H01L27/10897

摘要： A sense amplifier for use with a dynamic random access memory is formed in a silicon integrated circuit. The pitch of an array of such sense amplifiers is equal to the pitch of pairs of bit lines of a memory array. Each array of sense amplifiers is formed from four rows of transistors of a given n or p-channel type Metal Oxide Semiconductor (MOS) transistor having a U-shaped gate electrode. The gate electrode of the transistors in each row of transistors of the sense amplifier is offset from those in a previous row by a preselected amount. The bit lines passing through the sense amplifier are straight, with no offsets to affect photolithographic performance, and no protuberances to increase the capacitance of the bit lines. Such an array of sense amplifiers has a size equivalent to the minimum size of the pairs of bit lines, and thus does not cause any increase in the width of the array of memory cells.

摘要翻译： 在硅集成电路中形成用于动态随机存取存储器的读出放大器。 这种读出放大器的阵列的间距等于存储器阵列的位线对的间距。 每个读出放大器阵列由具有U形栅电极的给定n或p沟道型金属氧化物半导体（MOS）晶体管的四行晶体管形成。 读出放大器的每行晶体管中的晶体管的栅电极以预先选定的量偏离前一行。 通过读出放大器的位线是直的，没有偏移影响光刻性能，也没有突起增加位线的电容。 这种读出放大器阵列的尺寸等于位线对的最小尺寸，因此不会导致存储器单元阵列的宽度的任何增加。

公开(公告)号：US06430076B1

公开(公告)日：2002-08-06

申请号：US09964209

申请日：2001-09-26

申请人： Gerhard Mueller ,  Armin M. Reith

发明人： Gerhard Mueller ,  Armin M. Reith

IPC分类号： G11C502

CPC分类号： H01L27/0207 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-level signal line architecture having signal line pairs employing vertical twists to reduce couplings noise is disclosed. The signal line pairs are provided with open regions to accommodate offsets of twists of adjacent signal line pairs, thus reducing the line pitch of the signal lines. The open region is formed by removing a portion of the signal line in the upper level and locating that portion on another level above the upper level.

摘要翻译： 公开了一种具有使用垂直扭曲的信号线对以减少耦合噪声的多电平信号线架构。 信号线对设置有开放区域以适应相邻信号线对的扭曲偏移，从而减小信号线的线间距。 通过去除上层的信号线的一部分并将该部分定位在上层上方的另一层上而形成开放区域。

公开(公告)号：US06232154B1

公开(公告)日：2001-05-15

申请号：US09442890

申请日：1999-11-18

申请人： Armin M. Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

发明人： Armin M. Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

IPC分类号： H01L2182

CPC分类号： H01L28/40 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/10897

摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

摘要翻译： 使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。 该方法将自动或手动生成光刻填充图案与电容器的形成相结合。 根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。 然后，最近的电源网络被提取。 所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。 然后空的空间被分配适当的去耦电容。 通过该方法产生的去耦电容适用于降低噪声的VLSI电源。