Normally-off high electron mobility transistors
    1.
    发明授权
    Normally-off high electron mobility transistors 有权
    常关高电子迁移率晶体管

    公开(公告)号:US09373688B2

    公开(公告)日:2016-06-21

    申请号:US13100343

    申请日:2011-05-04

    摘要: A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.

    摘要翻译: 常闭晶体管包括III-V族半导体材料的第一区域,第一区域上的III-V族半导体材料的第二区域,第二区域上的III-V族半导体材料的第三区域和至少相邻的栅电极 第三区域的一个侧壁。 第一区域提供晶体管的通道。 第二区域具有比第一区域的带隙大的带隙,并且在通道中产生2-D电子气体(2DEG)。 第二区域介于第一区域和第三区域之间。 第三区域提供晶体管的栅极并且具有足以消耗沟道中的2DEG的厚度,使得晶体管具有正的阈值电压。

    Normally-Off High Electron Mobility Transistors
    2.
    发明申请
    Normally-Off High Electron Mobility Transistors 有权
    常关高电子迁移率晶体管

    公开(公告)号:US20120280278A1

    公开(公告)日:2012-11-08

    申请号:US13100343

    申请日:2011-05-04

    IPC分类号: H01L29/778 H01L21/335

    摘要: A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.

    摘要翻译: 常闭晶体管包括III-V族半导体材料的第一区域,第一区域上的III-V族半导体材料的第二区域,第二区域上的III-V族半导体材料的第三区域和至少相邻的栅电极 第三区域的一个侧壁。 第一区域提供晶体管的通道。 第二区域具有比第一区域的带隙大的带隙,并且在通道中产生2-D电子气体(2DEG)。 第二区域介于第一区域和第三区域之间。 第三区域提供晶体管的栅极并且具有足以消耗沟道中的2DEG的厚度,使得晶体管具有正的阈值电压。

    III-V Semiconductor Devices with Buried Contacts
    3.
    发明申请
    III-V Semiconductor Devices with Buried Contacts 有权
    具有埋地触点的III-V半导体器件

    公开(公告)号:US20130153919A1

    公开(公告)日:2013-06-20

    申请号:US13331899

    申请日:2011-12-20

    IPC分类号: H01L29/778 H01L21/335

    摘要: A semiconductor device such as a diode or transistor includes a semiconductor substrate, a first region of III-V semiconductor material on the semiconductor substrate and a second region of III-V semiconductor material on the first region. The second region is spaced apart from the semiconductor substrate by the first region. The second region is of a different composition than the first region. The semiconductor device further includes a buried contact extending from the semiconductor substrate to the second region through the first region. The buried contact electrically connects the second region to the semiconductor substrate.

    摘要翻译: 诸如二极管或晶体管的半导体器件包括半导体衬底,半导体衬底上的III-V半导体材料的第一区域和第一区域上的III-V半导体材料的第二区域。 第二区域与第一区域与半导体衬底间隔开。 第二区域具有与第一区域不同的组成。 半导体器件还包括从半导体衬底延伸穿过第一区域延伸到第二区域的埋入触点。 埋入式触点将第二区域电连接到半导体衬底。

    Contact Structures for Compound Semiconductor Devices
    4.
    发明申请
    Contact Structures for Compound Semiconductor Devices 有权
    复合半导体器件的接触结构

    公开(公告)号:US20130299842A1

    公开(公告)日:2013-11-14

    申请号:US13470771

    申请日:2012-05-14

    IPC分类号: H01L29/778 H01L29/66

    摘要: A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region.

    摘要翻译: 半导体器件包括半导体本体,其包括多个化合物半导体层和形成在化合物半导体层之一中的二维电荷载流子通道区域。 半导体器件还包括设置在半导体本体中的接触结构。 接触结构包括金属区域和掺杂区域。 金属区域从半导体本体的第一侧延伸到半导体本体至少包括沟道区的化合物半导体层。 掺杂区域形成在金属区域和沟道区域之间的半导体本体中,使得沟道区域通过掺杂区域电连接到金属区域。

    III-V semiconductor devices with buried contacts
    6.
    发明授权
    III-V semiconductor devices with buried contacts 有权
    具有埋地触点的III-V半导体器件

    公开(公告)号:US08569799B2

    公开(公告)日:2013-10-29

    申请号:US13331899

    申请日:2011-12-20

    IPC分类号: H01L29/66

    摘要: A semiconductor device such as a diode or transistor includes a semiconductor substrate, a first region of III-V semiconductor material on the semiconductor substrate and a second region of III-V semiconductor material on the first region. The second region is spaced apart from the semiconductor substrate by the first region. The second region is of a different composition than the first region. The semiconductor device further includes a buried contact extending from the semiconductor substrate to the second region through the first region. The buried contact electrically connects the second region to the semiconductor substrate.

    摘要翻译: 诸如二极管或晶体管的半导体器件包括半导体衬底,半导体衬底上的III-V半导体材料的第一区域和第一区域上的III-V半导体材料的第二区域。 第二区域与第一区域与半导体衬底间隔开。 第二区域具有与第一区域不同的组成。 半导体器件还包括从半导体衬底延伸穿过第一区域延伸到第二区域的埋入触点。 埋入式触点将第二区域电连接到半导体衬底。

    Normally-off compound semiconductor tunnel transistor
    7.
    发明授权
    Normally-off compound semiconductor tunnel transistor 有权
    常规化合物半导体隧道晶体管

    公开(公告)号:US08586993B2

    公开(公告)日:2013-11-19

    申请号:US13406568

    申请日:2012-02-28

    IPC分类号: H01L29/778

    摘要: Disclosed herein are embodiments of a normally-off compound semiconductor tunnel field effect transistor having a drive current above 100 mA per mm of gate length and a sub-threshold slope below 60 mV per decade at room temperature, and methods of manufacturing such a normally-off compound semiconductor tunnel transistor. The compound semiconductor tunnel field effect transistor is fast-switching and can be used for high voltage applications e.g. 30V up to 600V and higher.

    摘要翻译: 本文公开了常温化合物半导体隧道场效应晶体管的实施例,其具有每毫米栅极长度高于100mA的驱动电流和在室温下每十年低于60mV的次阈值斜率的制造方法, 关闭复合半导体隧道晶体管。 化合物半导体隧道场效应晶体管是快速切换的,并且可以用于高电压应用,例如 30V至600V及以上。

    NORMALLY-OFF COMPOUND SEMICONDUCTOR TUNNEL TRANSISTOR
    8.
    发明申请
    NORMALLY-OFF COMPOUND SEMICONDUCTOR TUNNEL TRANSISTOR 有权
    正常化合物半导体隧道晶体管

    公开(公告)号:US20130221366A1

    公开(公告)日:2013-08-29

    申请号:US13406568

    申请日:2012-02-28

    IPC分类号: H01L29/778 H01L21/335

    摘要: Disclosed herein are embodiments of a normally-off compound semiconductor tunnel field effect transistor having a drive current above 100 mA per mm of gate length and a sub-threshold slope below 60 mV per decade at room temperature, and methods of manufacturing such a normally-off compound semiconductor tunnel transistor. The compound semiconductor tunnel field effect transistor is fast-switching and can be used for high voltage applications e.g. 30V up to 600V and higher.

    摘要翻译: 本文公开了常温化合物半导体隧道场效应晶体管的实施例,其具有每毫米栅极长度高于100mA的驱动电流和在室温下每十年低于60mV的次阈值斜率的制造方法, 关闭复合半导体隧道晶体管。 化合物半导体隧道场效应晶体管是快速切换的,并且可以用于高电压应用,例如 30V至600V及以上。

    Compound Semiconductor Device with Buried Field Plate
    9.
    发明申请
    Compound Semiconductor Device with Buried Field Plate 有权
    具有掩埋场板的复合半导体器件

    公开(公告)号:US20130153967A1

    公开(公告)日:2013-06-20

    申请号:US13331970

    申请日:2011-12-20

    IPC分类号: H01L29/778 H01L21/20

    摘要: A semiconductor device includes a first compound semiconductor material and a second compound semiconductor material on the first compound semiconductor material. The second compound semiconductor material comprises a different material than the first compound semiconductor material such that the first compound semiconductor material has a two-dimensional electron gas (2DEG). The semiconductor device further includes a buried field plate disposed in the first compound semiconductor material and electrically connected to a terminal of the semiconductor device. The 2DEG is interposed between the buried field plate and the second compound semiconductor material.

    摘要翻译: 半导体器件在第一化合物半导体材料上包括第一化合物半导体材料和第二化合物半导体材料。 第二化合物半导体材料包含与第一化合物半导体材料不同的材料,使得第一化合物半导体材料具有二维电子气(2DEG)。 半导体器件还包括设置在第一化合物半导体材料中并与半导体器件的端子电连接的掩埋场板。 2DEG插入在掩埋场板和第二化合物半导体材料之间。

    Compound semiconductor transistor with self aligned gate
    10.
    发明授权
    Compound semiconductor transistor with self aligned gate 有权
    具有自对准栅极的复合半导体晶体管

    公开(公告)号:US09443941B2

    公开(公告)日:2016-09-13

    申请号:US13487698

    申请日:2012-06-04

    摘要: A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body. The transistor device further includes a source in contact with the two-dimensional charge carrier gas and a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas. A first passivation layer is in contact with the first surface of the compound semiconductor body, and a second passivation layer is disposed on the first passivation layer. The second passivation layer has a different etch rate selectivity than the first passivation layer. A gate extends through the second passivation layer into the first passivation layer.

    摘要翻译: 晶体管器件包括具有第一表面的化合物半导体本体和设置在化合物半导体本体中的第一表面下方的二维电荷载体气体。 晶体管器件还包括与二维电荷载气接触的源极和与源极间隔开并与二维电荷载气接触的漏极。 第一钝化层与化合物半导体本体的第一表面接触,第二钝化层设置在第一钝化层上。 第二钝化层具有与第一钝化层不同的蚀刻速率选择性。 栅极延伸穿过第二钝化层进入第一钝化层。