公开(公告)号：US4327477A

公开(公告)日：1982-05-04

申请号：US169559

申请日：1980-07-17

申请人： Giora Yaron ,  Eliyahou Harari ,  LaVerne D. Hess ,  Yueh Y. Ma

发明人： Giora Yaron ,  Eliyahou Harari ,  LaVerne D. Hess ,  Yueh Y. Ma

IPC分类号： H01L21/263 ,  H01L21/268 ,  H01L21/321 ,  B05D3/06

CPC分类号： H01L21/2636 ,  H01L21/268 ,  H01L21/321 ,  Y10S148/046

摘要： Defects in the metal step coverage of a thin film semiconductor device are removed by annealing the metal layer with a pulsed electron beam.

摘要翻译： 通过用脉冲电子束退火金属层来去除薄膜半导体器件的金属层覆盖的缺陷。

公开(公告)号：US5278439A

公开(公告)日：1994-01-11

申请号：US751499

申请日：1991-08-29

申请人： Yueh Y. Ma ,  Kuo-Tung Chang

发明人： Yueh Y. Ma ,  Kuo-Tung Chang

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0458

摘要： An EEPROM cell structure includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

摘要翻译： EEPROM单元结构包括由选择栅极晶体管隔开的两个浮栅晶体管，在编程，读取和擦除浮栅晶体管时，选择晶体管由两个浮栅晶体管共享。 两个晶体管的浮置栅极由第一多晶硅层形成，两个晶体管的控制栅极由第二多晶硅层形成，并且选择栅极由第三掺杂多晶硅层形成。 选择栅极晶体管的沟道长度与浮置栅极晶体管完全自对准。 在控制门上形成一条字线，形成选择门。 字线通常垂直于与两个浮栅晶体管的漏极区接触的位线。 因此，可以使用EEPROM单元结构来制造虚拟地闪存EEPROM存储器阵列。

公开(公告)号：US5414693A

公开(公告)日：1995-05-09

申请号：US269972

申请日：1994-07-01

申请人： Yueh Y. Ma ,  Kuo-Tung Chang

发明人： Yueh Y. Ma ,  Kuo-Tung Chang

IPC分类号： H01L21/8247 ,  G11C11/56 ,  G11C16/04 ,  H01L27/115 ,  H01L29/68 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0458

摘要： An EEPROM cell structure includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

摘要翻译： EEPROM单元结构包括由选择栅极晶体管隔开的两个浮栅晶体管，在编程，读取和擦除浮栅晶体管时，选择晶体管由两个浮栅晶体管共享。 两个晶体管的浮置栅极由第一多晶硅层形成，两个晶体管的控制栅极由第二多晶硅层形成，并且选择栅极由第三掺杂多晶硅层形成。 选择栅极晶体管的沟道长度与浮置栅极晶体管完全自对准。 在控制门上形成一条字线，形成选择门。 字线通常垂直于与两个浮栅晶体管的漏极区接触的位线。 因此，可以使用EEPROM单元结构来制造虚拟地闪存EEPROM存储器阵列。

公开(公告)号：US5663907A

公开(公告)日：1997-09-02

申请号：US639296

申请日：1996-04-25

申请人： Jack E. Frayer ,  John D. Lattanzi ,  Shouchang Tsao ,  Chan-Sui Pang ,  Yueh Y. Ma

发明人： Jack E. Frayer ,  John D. Lattanzi ,  Shouchang Tsao ,  Chan-Sui Pang ,  Yueh Y. Ma

IPC分类号： G11C16/30 ,  G11C11/34

CPC分类号： G11C16/30

摘要： For negative gate erase and programming of non-volatile floating gate EEPROM devices, large positive or negative voltages from one single negative charge pump and from one single positive charge pump are selectively switched onto a one or more memory sectors of twin-well CMOS negative-gate-erase memory cells. The control gate is negative during erasing and positive during programming. In order for FLASH memories to have minimum layout area, small sectors or arrays of EEPROM cells can be erased all at once using a charge pump which includes two pump capacitors to provide negative voltages to the gate terminals of one or more series PMOS transistors.

摘要翻译： 对于非挥发性浮置栅极EEPROM器件的负栅极擦除和编程，来自一个单个负电荷泵和一个单个正电荷泵的大的正或负电压被选择性地切换到双阱CMOS负极电荷泵的一个或多个存储器扇区， 门擦除存储单元。 擦除期间控制栅极为负，编程期间为正。 为了使FLASH存储器具有最小的布局面积，可以使用包括两个泵电容器的电荷泵一次清除小区或EEPROM阵列，以向一个或多个串联PMOS晶体管的栅极端提供负电压。

公开(公告)号：US5364806A

公开(公告)日：1994-11-15

申请号：US134779

申请日：1993-10-12

申请人： Yueh Y. Ma ,  Kuo-Tung Chang

发明人： Yueh Y. Ma ,  Kuo-Tung Chang

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/8247 ,  H01L21/265

CPC分类号： G11C11/5621 ,  G11C16/0458 ,  H01L27/11521

摘要： A method of making an EEPROM cell structure which includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

摘要翻译： 一种制造EEPROM单元结构的方法，其包括由选择栅晶体管分离的两个浮栅晶体管，其中选择晶体管在编程，读取和擦除浮栅晶体管时由两个浮栅晶体管共享。 两个晶体管的浮置栅极由第一多晶硅层形成，两个晶体管的控制栅极由第二多晶硅层形成，并且选择栅极由第三掺杂多晶硅层形成。 选择栅极晶体管的沟道长度与浮置栅极晶体管完全自对准。 在控制门上形成一条字线，形成选择门。 字线通常垂直于与两个浮栅晶体管的漏极区接触的位线。 因此，可以使用EEPROM单元结构来制造虚拟地闪存EEPROM存储器阵列。

公开(公告)号：US5280446A

公开(公告)日：1994-01-18

申请号：US895311

申请日：1992-06-08

申请人： Yueh Y. Ma ,  Kuo-Tung Chang

发明人： Yueh Y. Ma ,  Kuo-Tung Chang

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C11/40

CPC分类号： G11C16/3427 ,  G11C16/0408 ,  G11C16/0425 ,  H01L27/115

摘要： A flash EPROM memory array which operates at lower voltage power supply with no disturbance during operation. The memory circuit comprises a plurality of memory elements in a matrix fashion with each element including a semiconductor substrate, a drain region, a source region, a floating gate, a control gate, and a select gate. The low voltage power supply operation capability is achieved by a special arrangement on the said memory array such that the programming of the memory cell is achieved by high efficient hot electron injection which allows lower drain voltage during programming. No disturbance during program and erase occurs due to a control gate line running in parallel with the drain line. No disturbance access during read operation because of alternating drain and source lines such that the memory device can be read from the source side.

摘要翻译： 闪存EPROM存储器阵列，在低电压电源下工作，在运行期间无干扰。 存储电路包括矩阵方式的多个存储元件，每个元件包括半导体衬底，漏极区，源区，浮栅，控制栅和选择栅。 通过在所述存储器阵列上的特殊布置来实现低电压电源操作能力，使得通过高效热电子注入实现存储器单元的编程，其允许在编程期间降低漏极电压。 由于控制栅极线与漏极线并联运行，在编程和擦除期间不会发生干扰。 由于交流的漏极和源极线，读取操作期间无干扰，从而可以从源极读取存储器件。