公开(公告)号：US4327477A

公开(公告)日：1982-05-04

申请号：US169559

申请日：1980-07-17

申请人： Giora Yaron ,  Eliyahou Harari ,  LaVerne D. Hess ,  Yueh Y. Ma

发明人： Giora Yaron ,  Eliyahou Harari ,  LaVerne D. Hess ,  Yueh Y. Ma

IPC分类号： H01L21/263 ,  H01L21/268 ,  H01L21/321 ,  B05D3/06

CPC分类号： H01L21/2636 ,  H01L21/268 ,  H01L21/321 ,  Y10S148/046

摘要： Defects in the metal step coverage of a thin film semiconductor device are removed by annealing the metal layer with a pulsed electron beam.

摘要翻译： 通过用脉冲电子束退火金属层来去除薄膜半导体器件的金属层覆盖的缺陷。

公开(公告)号：US4341569A

公开(公告)日：1982-07-27

申请号：US166881

申请日：1980-07-08

申请人： Giora Yaron ,  Eliyahou Harari ,  Samuel T. Wang ,  LaVerne D. Hess

发明人： Giora Yaron ,  Eliyahou Harari ,  Samuel T. Wang ,  LaVerne D. Hess

IPC分类号： H01L21/268 ,  H01L21/768 ,  H01L21/263 ,  B05D3/06

CPC分类号： H01L21/268 ,  H01L21/76894

摘要： A beam of radiant energy such as a laser beam is applied to an epitaxial silicon island on a silicon on sapphire device before formation of overlying layers of oxide and metal. The energy beam changes the crystal structure of the epitaxial silicon island to increase the mobility of carriers in the silicon island, improving the speed of transistors formed on the silicon island. The energy beam also causes the material in the silicon island edge to reflow, causing a reduction in the slope of the edge face of the silicon island edge, and a smoothing of the surface of the face, resulting in improved aluminum step coverage and elimination of a V-shaped groove in the first insulation layer at the bottom corner edge of the island, thereby increasing processing yield.

摘要翻译： 在形成覆盖层的氧化物和金属之前，将诸如激光束的辐射能量束施加到蓝宝石器件上的硅上的外延硅岛上。 能量束改变外延硅岛的晶体结构，以增加硅岛中载流子的迁移率，从而提高在硅岛上形成的晶体管的速度。 能量束还导致硅岛边缘中的材料回流，导致硅岛边缘的边缘面的斜率减小，并且使表面的平滑化，导致改善的铝步骤覆盖和消除 在岛的底角边缘处的第一绝缘层中的V形槽，从而提高加工产量。

公开(公告)号：US09076518B2

公开(公告)日：2015-07-07

申请号：US13365991

申请日：2012-02-03

申请人： Roy E. Scheuerlein ,  Eliyahou Harari

发明人： Roy E. Scheuerlein ,  Eliyahou Harari

IPC分类号： H01L29/06 ,  G11C13/00 ,  G11C17/16 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C13/0007 ,  G11C13/0004 ,  G11C13/0011 ,  G11C17/16 ,  G11C2213/19 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/35 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/1675

摘要： A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

摘要翻译： 公开了一种三维非易失性存储器系统，其包括利用用于存储单元形成的共享柱结构的存储器阵列。 共享支柱结构包括两个非易失性存储元件。 每个柱的第一端表面与第一组阵列线接触一个阵列线，并且每个柱的第二端表面与第二组阵列线接触两个阵列线，所述第二组阵列线与第一组阵列线垂直分离。 每个支柱包括被分成用于支柱中的各个存储元件的部分的第一子层子集。 每个柱包括在形成在柱中的两个非易失性存储元件之间共享的层的第二子集。 各个存储元件各自包括转向元件和状态改变元件。

公开(公告)号：US08334180B2

公开(公告)日：2012-12-18

申请号：US13204533

申请日：2011-08-05

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

摘要翻译： 闪存NAND型EEPROM系统，其具有诸如浮置栅极的电荷存储元件阵列中的各个，与至少两个控制栅极线电容耦合。 控制栅极线优选地位于与浮动栅极的侧壁耦合的浮动栅极之间。 结果，期望地增加存储单元耦合比。 通常将所选行的浮置栅极的相对侧上的两个控制栅极线升高到相同的电压，而与所选行的紧邻和相对侧的未选择的浮动栅极行耦合的第二控制栅极线保持为低。 控制栅极线也可以与衬底电容耦合，以选择性地提高其在所选浮栅的区域中的电压。 通过形成间隔物的蚀刻掩模，可以使浮栅的长度和控制栅极线的厚度小于工艺的最小分辨率元件。

公开(公告)号：US08213519B2

公开(公告)日：2012-07-03

申请号：US12120253

申请日：2008-05-14

申请人： Moshe Raines ,  Eliyahou Harari ,  Ran Carmeli

发明人： Moshe Raines ,  Eliyahou Harari ,  Ran Carmeli

IPC分类号： H04N7/24 ,  G06K9/32 ,  G06T1/20

CPC分类号： H04N9/7921 ,  G06F1/3203 ,  G06F1/3293 ,  H04N5/775 ,  H04N5/907 ,  H04N9/8042 ,  H04N9/8047 ,  Y02D10/122

摘要： Methods of operating a portable media device 100 including two onboard hardware media decoders (124, 128) operative to decode a given digital content item 148 are disclosed. In some embodiments, one of the onboard hardware media decoders 128 has a relatively high power consumption and produces a relatively ‘high quality’ media signal, and the other of the onboard hardware media decoder 124 has a relatively low power consumption and produces a relatively ‘low quality’ media signal. In one non-limiting use case: (i) when no external power is available, the relatively ‘low power’ hardware media decoder 124 may generate a relatively ‘low quality’ media signal which is presented on an onboard display screen 140a and/or onboard speaker 140b; and (ii) when external power is available, the relatively ‘high power’ hardware media decoder 128 may generate a relatively ‘high quality’ media signal which is exported out of the portable media device 100 via one or more media ports, and presented on an external host presentation device 160 (for example, a large-screen television).

摘要翻译： 公开了操作便携式媒体设备100的方法，该便携式媒体设备100包括可操作以解码给定数字内容项目148的两个板上硬件媒体解码器（124,128）。 在一些实施例中，车载硬件介质解码器128中的一个具有相对高的功率消耗并产生相对“高品质”的媒体信号，并且车载硬件媒体解码器124中的另一个具有相对低的功率消耗并产生相对“ 低品质“媒体信号。 在一个非限制性使用情况下：（i）当没有外部电源可用时，相对“低功率”硬件媒体解码器124可以产生呈现在车载显示屏140a上的相对“低质量”媒体信号和/或 车载扬声器140b; 和（ii）当外部电源可用时，相对“高功率”的硬件媒体解码器128可以产生相对“高品质”的媒体信号，其通过一个或多个媒体端口从便携式媒体设备100导出， 外部主机呈现装置160（例如，大屏幕电视）。

公开(公告)号：US20120061459A1

公开(公告)日：2012-03-15

申请号：US13209788

申请日：2011-08-15

申请人： Eliyahou Harari ,  Yoram Cedar ,  Wesley G. Brewer ,  Yosi Pinto ,  Reuven Elhamias ,  Micky Holtzman

发明人： Eliyahou Harari ,  Yoram Cedar ,  Wesley G. Brewer ,  Yosi Pinto ,  Reuven Elhamias ,  Micky Holtzman

IPC分类号： G06K19/067 ,  G06F17/00

CPC分类号： G06K19/07 ,  G06K19/0719 ,  G06K19/077 ,  G06K19/07732 ,  G06K19/07733 ,  G06K19/07743

摘要： A memory card of one published standard, such as the Multi-Media Card (MMC) or Secure Digital Card (SD), is modified to include the function of a Subscriber Identity Module (SIM) according to another published standard. The controller of the memory card communicates between electrical contacts on the outside of the card and both the memory and the SIM. In one specific form, the memory card has the physical configuration of the current Plug-in SIM card with a few external contacts added to accommodate the memory controller and data memory. In another specific form, the memory card has the physical configuration of the current SD card, including external contacts.

摘要翻译： 根据另一个发布的标准，修改了一个已发布标准的存储卡，例如多媒体卡（MMC）或安全数字卡（SD））以包括订户身份模块（SIM）的功能。 存储卡的控制器在卡的外部的电触点和存储器和SIM卡之间通信。 在一种具体形式中，存储卡具有当前插件SIM卡的物理配置，其中添加了少量外部联系以容纳存储器控制器和数据存储器。 在另一个具体形式中，存储卡具有当前SD卡的物理配置，包括外部触点。

公开(公告)号：US20110287619A1

公开(公告)日：2011-11-24

申请号：US13204533

申请日：2011-08-05

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

摘要翻译： 闪存NAND型EEPROM系统，其具有诸如浮置栅极的电荷存储元件阵列中的各个，与至少两个控制栅极线电容耦合。 控制栅极线优选地位于与浮动栅极的侧壁耦合的浮动栅极之间。 结果，期望地增加存储单元耦合比。 通常将所选行的浮置栅极的相对侧上的两个控制栅极线升高到相同的电压，而与所选行的紧邻和相对侧的未选择的浮动栅极行耦合的第二控制栅极线保持为低。 控制栅极线也可以与衬底电容耦合，以选择性地提高其在所选浮栅的区域中的电压。 通过形成间隔物的蚀刻掩模，可以使浮栅的长度和控制栅极线的厚度小于工艺的最小分辨率元件。

公开(公告)号：US08040727B1

公开(公告)日：2011-10-18

申请号：US09143233

申请日：1998-08-28

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： G11C16/06

CPC分类号： G11C29/52 ,  G06F3/0616 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/123 ,  G06F2212/312 ,  G11C7/1039 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C29/765 ,  G11C29/82 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5643

摘要： A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

摘要翻译： 具有控制电路的闪存EEprom存储器芯片的系统用作诸如由磁盘驱动器提供的非易失性存储器。 改进包括选择性多扇区擦除，其中Flash扇区的任何组合可以一起被擦除。 所选组合中的选择扇区也可以在擦除操作期间被取消选择。 另一个改进是使用替代细胞重新映射和替换有缺陷的细胞的能力。 一旦检测到有缺陷的单元，就会自动执行重新映射。 当Flash扇区的缺陷数量变大时，整个扇区被重新映射。 另一个改进是使用写高速缓存来减少写入闪存EEPROM存储器的数量，从而最小化对器件进行过多写/擦循环的应力。

公开(公告)号：US08027165B2

公开(公告)日：2011-09-27

申请号：US10888599

申请日：2004-07-08

申请人： Robert F. Wallace ,  Edwin J. Cuellar ,  Eliyahou Harari ,  Yoram Cedar

发明人： Robert F. Wallace ,  Edwin J. Cuellar ,  Eliyahou Harari ,  Yoram Cedar

IPC分类号： H05K1/14

CPC分类号： G06K19/07732 ,  G06K19/0723

摘要： A flash memory card structure with an external contact structure according to a published standard, such as the USB standard, also includes a second data transmission path, such as a wireless one. A removable cap fits over the card to cover the external contacts when they are not being used as a memory data path. One of two or more different caps may be selected to be placed on the card in order to control operation of the second data transmission path, such as to select the distance of wireless transmission from one of two or more pre-set distances. Power to operate the memory card through the second path, when not connected to a host, may also be provided through the external contacts by including a battery in the caps.

摘要翻译： 具有诸如USB标准的公开标准的具有外部接触结构的闪存卡结构还包括诸如无线的第二数据传输路径。 当不被用作存储器数据路径时，可拆卸的盖子可以卡在卡上以覆盖外部触点。 可以选择将两个或更多个不同的盖中的一个放置在卡上以便控制第二数据传输路径的操作，例如从两个或更多个预定距离之一选择无线传输的距离。 通过在电池盖中包含电池，也可以通过外部触点提供未连接到主机时通过第二路径操作存储卡的电源。

公开(公告)号：US20110041039A1

公开(公告)日：2011-02-17

申请号：US12539394

申请日：2009-08-11

申请人： Eliyahou Harari ,  Richard R. Heye ,  Robert D. Selinger

发明人： Eliyahou Harari ,  Richard R. Heye ,  Robert D. Selinger

IPC分类号： G06F12/02 ,  H03M13/05 ,  G06F11/10 ,  G06F12/14

CPC分类号： G06F11/1068 ,  G06F12/0246 ,  G06F2212/7211 ,  G11C29/76 ,  G11C29/84

摘要： The embodiments described herein provide a controller and method for interfacing between a host controller in a host and a flash memory device. In one embodiment, a controller comprises a first NAND interface, a second NAND interface, and one or more of the following modules: a data scrambling module, a column replacement module, and a module that manages at least one of bad blocks and spare blocks. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

摘要翻译： 这里描述的实施例提供了用于在主机中的主机控制器和闪存设备之间进行接口的控制器和方法。 在一个实施例中，控制器包括第一NAND接口，第二NAND接口和以下模块中的一个或多个：数据加扰模块，列替换模块和管理坏块和备用块中的至少一个的模块 。 公开了其它实施例，并且每个实施例可以单独使用或组合使用。