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公开(公告)号：US06169423A
公开(公告)日：2001-01-02
申请号：US09186496
申请日：1998-11-04
IPC分类号： H03K522
CPC分类号： G11C8/18
摘要： The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.
摘要翻译： 本发明涉及一种用于调整半导体集成电子存储器件中存储单元读取相位的脉冲同步信号（ATD）的方法和电路。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD），以便还产生到读出放大器的均衡信号（SAEQ）。 当行电压达到预定的足够值时，SAEQ脉冲被阻塞（STOP），以提供可靠的读数。 有利地，通过在寻址的存储器行的过载阶段期间超过预定电压值而激活的逻辑信号（STOP）产生脉冲阻塞。
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公开(公告)号：US06456530B1
公开(公告)日：2002-09-24
申请号：US09602680
申请日：2000-06-26
IPC分类号： G11C1604
摘要： The memory device has hierarchical sector decoding. A plurality of groups of supply lines is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages are each connected between a respective sector and a respective group of supply lines; the switching stages connected to sectors arranged on a same column are controlled by same control signals supplied on control lines extending parallel to the columns of sectors. For biasing the sectors, modification voltages are sent to at least one selected group of biasing lines, and control signals are sent to the switching stages connected to a selected sector column.
摘要翻译： 存储器件具有分级扇区解码。 提供多组供应管线，每个扇区行一个平行于扇区行延伸。 多个开关级各自连接在相应的扇区和相应的一组供电线之间; 连接到布置在同一列上的扇区的开关级由与扇区列平行延伸的控制线上提供的相同控制信号控制。 为了偏置扇区，修改电压被发送到至少一组选定的偏置线，并且控制信号被发送到连接到所选扇区列的切换级。
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3.发明授权Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 有权用于产生ATD信号以调节对非易失性存储器的访问的方法和电路
公开(公告)号：US6075750A
公开(公告)日：2000-06-13
申请号：US186497
申请日：1998-11-04
CPC分类号： G11C8/18
摘要： A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.
摘要翻译： 一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。 该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。
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公开(公告)号：US06437636B2
公开(公告)日：2002-08-20
申请号：US09747312
申请日：2000-12-22
申请人： Matteo Zammattio , Ilaria Motta , Rino Micheloni , Carla Golla
发明人： Matteo Zammattio , Ilaria Motta , Rino Micheloni , Carla Golla
IPC分类号： G05F110
摘要： A voltage boost device includes a first boost stage and a second boost stage connected to an input terminal and to an output terminal, the output terminal supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage is enabled in presence of the second logic level of the operating condition signal, and is disabled in presence of the first logic level of the operating condition signal; the second boost stage is controlled in a first operating condition in presence of the first logic level of the operating condition signal, and is controlled in a second operating condition in presence of the second logic level of the operating condition signal.
摘要翻译： 升压装置包括连接到输入端子和输出端子的第一升压级和第二升压级，输出端子提供高于电源电压的输出电压。 输入端子接收具有代表待机操作状态的第一逻辑电平的操作状态信号和表示主动操作状态的第二逻辑电平。 第一升压级在存在操作条件信号的第二逻辑电平的情况下使能，并且在存在操作条件信号的第一逻辑电平的情况下禁用; 第二升压级在操作状态信号的第一逻辑电平存在的情况下在第一操作条件下被控制，并且在存在操作条件信号的第二逻辑电平的情况下被控制在第二操作状态。
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公开(公告)号：US5923076A
公开(公告)日：1999-07-13
申请号：US811577
申请日：1997-03-05
IPC分类号： H01L23/485 , H01L29/78
CPC分类号： H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/12036 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： An integrated device having an N-type well region formed in a P-type substrate and an N.sup.+ type contact ring housed in the well region. The well region forms respective capacitors with a conductive layer superimposed on the substrate, and with the substrate itself. The conductive layer and the substrate are grounded, and the contact ring is connected to the supply, so that the two capacitors are in parallel to each other and, together with the internal resistance of the well region, form a filter for stabilizing the supply voltage. When connected to an input buffer stage of the device, the filter provides for damping the peaks produced on the supply line of the input buffer by high-current switching of the output buffers.
摘要翻译： 具有形成在P型衬底中的N型阱区和容纳在阱区中的N +型接触环的集成器件。 阱区形成具有叠加在衬底上的导电层以及衬底本身的各个电容器。 导电层和基板接地，接触环连接到电源，使得两个电容器彼此平行，并且与阱区域的内部电阻一起形成用于稳定电源电压的滤波器 。 当连接到器件的输入缓冲级时，滤波器通过输出缓冲器的高电流切换来提供阻尼输入缓冲器电源线上产生的峰值。
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公开(公告)号：US5815464A
公开(公告)日：1998-09-29
申请号：US811869
申请日：1997-03-05
IPC分类号： G11C8/18 , H03K5/1534 , G11C7/00
CPC分类号： H03K5/1534 , G11C8/18
摘要： An address transition detection circuit having a number of cells supplied with respective address signals and outputs connected in a wired NOR configuration to generate a pulse signal on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage for generating an end-of-transition signal with a predetermined delay following reception of the pulse signal; and an output stage connected to the cells and to the monostable stage, which generates the first switching edge of the address transition signal on receiving the pulse signal, and the second switching edge on receiving the end-of-transition signal. The monostable stage presents a compensating structure for maintaining the delay in the switching of the end-of-transition signal despite variations in temperature and supply voltage.
摘要翻译： 一种地址转换检测电路，其具有提供有相应地址信号的单元的数量，并且以线性NOR配置连接的输出，以在检测各自地址信号的转变时产生脉冲信号。 脉冲信号被提供给源级，用于在接收脉冲信号时产生具有第一和第二开关沿的地址转换信号。 源级具有用于在接收到脉冲信号之后以预定延迟产生转换终止信号的单稳态级; 以及连接到单元和单稳态级的输出级，其在接收到脉冲信号时产生地址转换信号的第一开关沿，并且在接收到转换终止信号时产生第二开关沿。 单稳态阶段提供了一种补偿结构，用于尽管温度和电源电压有变化，仍保持转换终止信号的切换延迟。
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7.发明授权Memory cell voltage regulator with temperature correlated voltage generator circuit 有权具有温度相关电压发生器电路的存储单元稳压器公开(公告)号：US06184670B2
公开(公告)日：2001-02-06
申请号：US09186498
申请日：1998-11-04
IPC分类号： G05F316
CPC分类号： G05F3/245 , Y10S323/907
摘要： A temperature-related voltage generating circuit has an input terminal receiving a control voltage independent of temperature, and an output terminal delivering a temperature-related control voltage. The input and output terminals are connected together through at least an amplifier stage adapted to set an output reference voltage from a comparison of input voltages. The voltage generating circuit also includes a generator element generating a varying voltage with temperature and connected between a ground voltage reference and a non-inverting input terminal of the amplifier stage. The amplifier stage has an output terminal adapted to deliver a multiple of the varying voltage with temperature to an inverting input terminal of a comparator stage. The comparator stage has its output connected to the temperature-related voltage generating circuit and a non-inverting input terminal receiving the control voltage independent of temperature to evaluate the difference between the control voltage independent of temperature and said voltage being a multiple of the varying voltage with temperature and to output a temperature-related control voltage having at room temperature a mean value which is independent of its thermal differential and increases with temperature. The voltage generating circuit can be incorporated into a regulator for a drain voltage of a single-supply memory cell.
摘要翻译： 温度相关电压发生电路具有接收与温度无关的控制电压的输入端子和输出与温度有关的控制电压的输出端子。 输入和输出端子通过至少一个放大器级连接在一起，适用于根据输入电压的比较设置输出参考电压。 电压产生电路还包括发生器元件，其产生具有温度的变化的电压并且连接在放大器级的接地电压基准和非反相输入端子之间。 放大器级具有输出端子，其适于将变化的温度的电压的倍数传送到比较器级的反相输入端子。 比较器级的输出端连接到温度相关的电压产生电路，而非反相输入端子接收与温度无关的控制电压，以评估与温度无关的控制电压之间的差值，而所述电压是变化电压的倍数 并且输出具有在室温下的温度相关控制电压，其平均值与其热差异无关并随温度升高。 电压发生电路可以并入用于单电源存储单元的漏极电压的调节器中。
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公开(公告)号：US6064598A
公开(公告)日：2000-05-16
申请号：US275694
申请日：1999-03-24
CPC分类号： G11C16/12
摘要： A switching circuit comprising a supply voltage, a reference voltage, a line suitable to carry a negative voltage, an input for a control signal, suitable to supply to a first output node and to a second output node two voltages respectively equal to supply voltage and to line voltage or, alternatively, to line voltage and to supply voltage, in response to the control signal. There are first interrupting means, second interrupting means, third interrupting means, fourth interrupting means, the first and third interrupting means connected in series between the supply voltage and the line, the second and fourth interrupting means connected in series with each other and in parallel to first and third interrupting means, the first output node corresponding to common node between the first interrupting means and the third interrupting means, the second output node corresponding to common node between the second interrupting means and the fourth interrupting means, the control signal controlling first interrupting means and second interrupting means in such a way that when the first interrupting means are open, also the fourth interrupting means are open whereas the second interrupting means and third interrupting means are closed, connecting the first output node to line and the second output node to supply voltage, and vice versa when the first interrupting means are closed, also fourth interrupting means are closed whereas the second interrupting means and third interrupting means are open, connecting the first output node to supply voltage and the second output node to line.
摘要翻译： 一种开关电路，包括电源电压，参考电压，适于承载负电压的线路，用于控制信号的输入端，适于向第一输出节点和第二输出节点提供分别等于电源电压的两个电压和 或者作为线路电压，并且响应于控制信号而提供电压。 第一中断装置，第二中断装置，第三中断装置，第四中断装置，串联连接在电源电压和线路之间的第一和第三中断装置，第二和第四中断装置彼此串联并联 对于第一和第三中断装置，对应于第一中断装置和第三中断装置之间的公共节点的第一输出节点，对应于第二中断装置和第四中断装置之间的公共节点的第二输出节点，控制信号 中断装置和第二中断装置，使得当第一中断装置打开时，第四中断装置也打开，而第二中断装置和第三中断装置关闭，将第一输出节点连接到线路，第二输出节点 提供电压，反之亦然，当第一次中断时 ns闭合，第四中断装置闭合，而第二中断装置和第三中断装置断开，将第一输出节点连接到电源电压，将第二输出节点连接到线路。
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9.发明授权
公开(公告)号：US6097213A
公开(公告)日：2000-08-01
申请号：US275691
申请日：1999-03-24
IPC分类号： G11C5/14 , G11C16/30 , H03K19/0948
摘要： Switching circuit comprising a reference voltage, an input voltage, suitable to assume alternatively a negative value or a value equal to said reference voltage, an output node, suitable to assume selectively three possible voltage values equal to a supply voltage, to the reference voltage, to the input voltage or, alternatively, to be kept floating, in response to a first, a second, a third, a fourth, a fifth, a sixth control logic signal, switching between the supply voltage and the reference voltage.
摘要翻译： 开关电路包括参考电压，适于替代地假定为负值或等于所述参考电压的输入电压;输出节点，适于选择等于电源电压的三个可能的电压值与参考电压， 响应于第一，第二，第三，第四，第五，第六，第六，第五，第六控制逻辑信号，在电源电压和参考电压之间切换，或者备选地保持浮置。
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公开(公告)号：US5955873A
公开(公告)日：1999-09-21
申请号：US960844
申请日：1997-10-30
CPC分类号： G05F3/30 , G05F3/26 , Y10S323/901 , Y10S323/907
摘要： A band-gap reference voltage generator comprises an operational amplifier comprising a first input and a second input, the first input being coupled to a first feedback network and the second input being coupled to a second feedback network both coupled to an output of the operational amplifier providing a reference voltage. The first feedback network contains an emitter-base junction of first bipolar junction transistor and the second feedback network contains an emitter-base junction of second bipolar junction transistor. A selectively activated current supply supplies a bias current to the operational amplifier, the current supply being deactivatable in a substantially zero power consumption operating condition for turning the reference voltage generator off. A start-up circuit activated upon start-up of the reference voltage generator for a fixed, prescribed time interval forces a start-up current to flow through the first bipolar junction transistor means.
摘要翻译： 带隙参考电压发生器包括运算放大器，其包括第一输入端和第二输入端，第一输入端耦合到第一反馈网络，第二输入端耦合到第二反馈网络，二者耦合到运算放大器的输出端 提供参考电压。 第一反馈网络包含第一双极结晶体管的发射极 - 基极结，并且第二反馈网络包含第二双极结型晶体管的发射极 - 基极结。 选择性地激活的电流源向运算放大器提供偏置电流，电流源可在基本为零的功耗操作条件下停用，用于使参考电压发生器关闭。 在参考电压发生器启动固定的规定时间间隔时启动的启动电路迫使启动电流流过第一双极结型晶体管装置。
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