公开(公告)号：US06437636B2

公开(公告)日：2002-08-20

申请号：US09747312

申请日：2000-12-22

申请人： Matteo Zammattio ,  Ilaria Motta ,  Rino Micheloni ,  Carla Golla

发明人： Matteo Zammattio ,  Ilaria Motta ,  Rino Micheloni ,  Carla Golla

IPC分类号： G05F110

CPC分类号： G11C16/30 ,  G11C5/145

摘要： A voltage boost device includes a first boost stage and a second boost stage connected to an input terminal and to an output terminal, the output terminal supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage is enabled in presence of the second logic level of the operating condition signal, and is disabled in presence of the first logic level of the operating condition signal; the second boost stage is controlled in a first operating condition in presence of the first logic level of the operating condition signal, and is controlled in a second operating condition in presence of the second logic level of the operating condition signal.

摘要翻译： 升压装置包括连接到输入端子和输出端子的第一升压级和第二升压级，输出端子提供高于电源电压的输出电压。 输入端子接收具有代表待机操作状态的第一逻辑电平的操作状态信号和表示主动操作状态的第二逻辑电平。 第一升压级在存在操作条件信号的第二逻辑电平的情况下使能，并且在存在操作条件信号的第一逻辑电平的情况下禁用; 第二升压级在操作状态信号的第一逻辑电平存在的情况下在第一操作条件下被控制，并且在存在操作条件信号的第二逻辑电平的情况下被控制在第二操作状态。

公开(公告)号：US06169423A

公开(公告)日：2001-01-02

申请号：US09186496

申请日：1998-11-04

申请人： Giovanni Campardo ,  Rino Micheloni ,  Matteo Zammattio ,  Donato Ferrario

发明人： Giovanni Campardo ,  Rino Micheloni ,  Matteo Zammattio ,  Donato Ferrario

IPC分类号： H03K522

CPC分类号： G11C8/18

摘要： The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

摘要翻译： 本发明涉及一种用于调整半导体集成电子存储器件中存储单元读取相位的脉冲同步信号（ATD）的方法和电路。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD），以便还产生到读出放大器的均衡信号（SAEQ）。 当行电压达到预定的足够值时，SAEQ脉冲被阻塞（STOP），以提供可靠的读数。 有利地，通过在寻址的存储器行的过载阶段期间超过预定电压值而激活的逻辑信号（STOP）产生脉冲阻塞。

公开(公告)号：US06456530B1

公开(公告)日：2002-09-24

申请号：US09602680

申请日：2000-06-26

申请人： Rino Micheloni ,  Matteo Zammattio ,  Giovanni Campardo

发明人： Rino Micheloni ,  Matteo Zammattio ,  Giovanni Campardo

IPC分类号： G11C1604

CPC分类号： G11C8/12 ,  G11C16/12

摘要： The memory device has hierarchical sector decoding. A plurality of groups of supply lines is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages are each connected between a respective sector and a respective group of supply lines; the switching stages connected to sectors arranged on a same column are controlled by same control signals supplied on control lines extending parallel to the columns of sectors. For biasing the sectors, modification voltages are sent to at least one selected group of biasing lines, and control signals are sent to the switching stages connected to a selected sector column.

摘要翻译： 存储器件具有分级扇区解码。 提供多组供应管线，每个扇区行一个平行于扇区行延伸。 多个开关级各自连接在相应的扇区和相应的一组供电线之间; 连接到布置在同一列上的扇区的开关级由与扇区列平行延伸的控制线上提供的相同控制信号控制。 为了偏置扇区，修改电压被发送到至少一组选定的偏置线，并且控制信号被发送到连接到所选扇区列的切换级。

公开(公告)号：US6075750A

公开(公告)日：2000-06-13

申请号：US186497

申请日：1998-11-04

申请人： Giovanni Campardo ,  Rino Micheloni ,  Marco Maccarrone ,  Matteo Zammattio

发明人： Giovanni Campardo ,  Rino Micheloni ,  Marco Maccarrone ,  Matteo Zammattio

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C8/18

摘要： A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.

摘要翻译： 一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。 该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。

公开(公告)号：US06249112B1

公开(公告)日：2001-06-19

申请号：US09608445

申请日：2000-06-29

申请人： Osama Khouri ,  Rino Micheloni ,  Ilaria Motta ,  Guido Torelli

发明人： Osama Khouri ,  Rino Micheloni ,  Ilaria Motta ,  Guido Torelli

IPC分类号： G05F140

CPC分类号： G05F3/242

摘要： Presented is a voltage regulating circuit for a capacitive load, which is connected between first and second terminals of a supply voltage generator. The regulating circuit has an input terminal and an output terminal, and includes an operational amplifier having an inverting input terminal connected to the input terminal of the regulating circuit and a non-inverting input terminal connected to an intermediate node of a voltage divider. The voltage divider is connected between an output node, which is connected to the output terminal of the regulating circuit, and the second terminal of the supply voltage generator. The operational amplifier has an output terminal connected, for driving a first field-effect transistor, between the output node and the first terminal of the supply voltage generator. The output terminal of the operational amplifier is also connected to the output node through a compensation network. The voltage regulating circuit also includes a second field-effect transistor connected between the output node and the second terminal of the supply voltage generator, which has its gate terminal connected to a constant voltage generating circuit means.

摘要翻译： 提出了一种用于容性负载的电压调节电路，其连接在电源电压发生器的第一和第二端子之间。 调节电路具有输入端子和输出端子，并且包括具有连接到调节电路的输入端子的反相输入端子和连接到分压器的中间节点的非反相输入端子的运算放大器。 分压器连接在与调节电路的输出端子连接的输出节点和电源电压发生器的第二端子之间。 运算放大器在输出节点和电源电压发生器的第一端之间连接有用于驱动第一场效应晶体管的输出端子。 运算放大器的输出端也通过补偿网络连接到输出节点。 电压调节电路还包括连接在电源电压发生器的输出节点和第二端子之间的第二场效应晶体管，其栅极端子连接到恒压产生电路装置。

公开(公告)号：US06822905B2

公开(公告)日：2004-11-23

申请号：US10331106

申请日：2002-12-27

申请人： Rino Micheloni ,  Ilaria Motta

发明人： Rino Micheloni ,  Ilaria Motta

IPC分类号： G11C1606

CPC分类号： G11C16/30

摘要： A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a reference current. A fraction of the source current is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels. The comparison may be used for controlling a current generator to inject, into the source terminal, the current necessary to keep the predetermined voltage thereof at a constant value.

摘要翻译： 一种方法和电路用于在单元编程和/或读取阶段期间调节非易失性存储单元的源极端子电压。 该方法包括局部调节电压值的相位，并且包括将电池阵列的源电流与参考电流进行比较。 将源电流的一部分转换成电压，并将其与作为参考的存储器单元产生的电压进行比较，并将其编程为具有最高电流电平的分布。 比较可以用于控制电流发生器向源极端子注入将其预定电压保持在恒定值所需的电流。

公开(公告)号：US06809961B2

公开(公告)日：2004-10-26

申请号：US10331116

申请日：2002-12-27

申请人： Rino Micheloni ,  Sabina Mognoni ,  Ilaria Motta ,  Andrea Sacco

发明人： Rino Micheloni ,  Sabina Mognoni ,  Ilaria Motta ,  Andrea Sacco

IPC分类号： G11C1604

CPC分类号： G11C16/30

摘要： A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.

摘要翻译： 一种方法和程序加载电路用于调节正被编程的非易失性存储单元的漏极和体端子处的电压。 这些电压从连接在导通图案中的编程负载电路施加，以将预定的电压值传送到存储单元的至少一个端子。 该方法包括在编程负载电路内局部调节电压值以克服存在于导电图案中的寄生电阻的影响的步骤。

公开(公告)号：US06259635B1

公开(公告)日：2001-07-10

申请号：US09491476

申请日：2000-01-19

申请人： Osama Khouri ,  Rino Micheloni ,  Ilaria Motta ,  Andrea Sacco ,  Guido Torelli

发明人： Osama Khouri ,  Rino Micheloni ,  Ilaria Motta ,  Andrea Sacco ,  Guido Torelli

IPC分类号： G11C1604

CPC分类号： G11C16/26 ,  G11C5/145 ,  G11C8/08 ,  G11C8/14 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/30

摘要： A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.

摘要翻译： 一种用于调节存储器中的字线电压的电路，包括适于在选择一个或多个字线时产生要提供给存储器的一个或多个字线的输出调节电压的电压调节器。 该电路包括一个升压电路，其耦合到所述电压调节器的输出端，并且可以在选择一个或多个存储器字线时被激活，以便在选择一个或多个存储器字线时升高调节电压 。

公开(公告)号：US07394694B2

公开(公告)日：2008-07-01

申请号：US11445491

申请日：2006-05-31

申请人： Rino Micheloni ,  Roberto Ravasio ,  Ilaria Motta

发明人： Rino Micheloni ,  Roberto Ravasio ,  Ilaria Motta

IPC分类号： G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/3409

摘要： A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.

摘要翻译： NAND闪速存储器件包括每个具有阈值电压的存储器单元矩阵。 矩阵包括单独的可擦除扇区，并且被布置成多行和列，其中每列的单元被排列成串联连接的多个单元格单元。 存储器件包括擦除所选扇区的单元的逻辑，以及恢复已擦除单元的阈值电压的恢复逻辑。 恢复逻辑依次作用于扇区的多个块中的每个块，每个块包括一个或多个单元的组。 恢复逻辑相对于超过读取参考值的限制值读取每个组，仅对至少一个单元的阈值电压没有达到极限值的每个组进行编程，并且响应于达到极限值而停止恢复 至少一组这些组。

公开(公告)号：US06259632B1

公开(公告)日：2001-07-10

申请号：US09491475

申请日：2000-01-19

申请人： Osama Khouri ,  Rino Micheloni ,  Ilaria Motta ,  Andrea Sacco ,  Guido Torelli

发明人： Osama Khouri ,  Rino Micheloni ,  Ilaria Motta ,  Andrea Sacco ,  Guido Torelli

IPC分类号： G11C1606

CPC分类号： G11C11/5621 ,  G11C8/14 ,  G11C16/08 ,  G11C16/30

摘要： Circuit for the regulation of the word line voltage in a memory, including a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when said one or more word lines are being selected, and charge accumulation means that are selectively connectable with the output of the voltage regulator and suitable to accumulate a compensation charge for a voltage drop that takes place on said regulated voltage upon the selection of said one or more word lines of the memory.

摘要翻译： 用于调节存储器中的字线电压的电路，包括适于在选择所述一个或多个字线时产生要提供给存储器的一个或多个字线的输出调节电压的电压调节器，以及电荷累积 意味着可以选择性地与电压调节器的输出端连接，并且适合于在选择存储器的所述一个或多个字线时，对在所述调节电压上发生的电压降累积补偿电荷。