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公开(公告)号：US06169423A
公开(公告)日：2001-01-02
申请号：US09186496
申请日：1998-11-04
IPC分类号： H03K522
CPC分类号： G11C8/18
摘要： The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.
摘要翻译： 本发明涉及一种用于调整半导体集成电子存储器件中存储单元读取相位的脉冲同步信号（ATD）的方法和电路。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD），以便还产生到读出放大器的均衡信号（SAEQ）。 当行电压达到预定的足够值时，SAEQ脉冲被阻塞（STOP），以提供可靠的读数。 有利地，通过在寻址的存储器行的过载阶段期间超过预定电压值而激活的逻辑信号（STOP）产生脉冲阻塞。
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公开(公告)号：US06456530B1
公开(公告)日：2002-09-24
申请号：US09602680
申请日：2000-06-26
IPC分类号： G11C1604
摘要： The memory device has hierarchical sector decoding. A plurality of groups of supply lines is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages are each connected between a respective sector and a respective group of supply lines; the switching stages connected to sectors arranged on a same column are controlled by same control signals supplied on control lines extending parallel to the columns of sectors. For biasing the sectors, modification voltages are sent to at least one selected group of biasing lines, and control signals are sent to the switching stages connected to a selected sector column.
摘要翻译： 存储器件具有分级扇区解码。 提供多组供应管线，每个扇区行一个平行于扇区行延伸。 多个开关级各自连接在相应的扇区和相应的一组供电线之间; 连接到布置在同一列上的扇区的开关级由与扇区列平行延伸的控制线上提供的相同控制信号控制。 为了偏置扇区，修改电压被发送到至少一组选定的偏置线，并且控制信号被发送到连接到所选扇区列的切换级。
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3.发明授权Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 有权用于产生ATD信号以调节对非易失性存储器的访问的方法和电路
公开(公告)号：US6075750A
公开(公告)日：2000-06-13
申请号：US186497
申请日：1998-11-04
CPC分类号： G11C8/18
摘要： A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.
摘要翻译： 一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。 该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。
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4.发明授权Voltage regulator or non-volatile memories implemented with low-voltage transistors 有权用低压晶体管实现的稳压器或非易失性存储器公开(公告)号：US07777466B2
公开(公告)日：2010-08-17
申请号：US11844470
申请日：2007-08-24
IPC分类号： G05F1/40
摘要： A voltage regulator integrated in a chip of semiconductor material is provided. The regulator has a first input terminal for receiving a first voltage and an output terminal for providing a regulated voltage being obtained from the first voltage, the regulator including: a differential amplifier for receiving a comparison voltage and a feedback signal being a function of the regulated voltage, and for proving a regulation signal according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means for controlling the auxiliary transistors according to the regulated voltage.
摘要翻译： 提供集成在半导体材料芯片中的电压调节器。 所述调节器具有用于接收第一电压的第一输入端子和用于提供从所述第一电压获得的调节电压的输出端子，所述调节器包括：用于接收比较电压的差分放大器和作为所述第一电压的函数的反馈信号 电压，并且为了根据比较电压和反馈信号之间的比较来证明调节信号，差分放大器具有与用于接收参考电压的参考端子耦合的第一电源端子和第二电源端子，调节晶体管具有 用于接收所述调节信号的控制端子，以及通过所述参考端子和所述调节器的所述第一输入端子之间的负载装置耦合的导通第一端子和导通第二端子，所述调节晶体管的所述第二端子与所述输出端子 的调节器，其中第二电源 差分放大器的nal与调节器的第二输入端耦合，用于接收低于绝对值中的第一电压的第二电压，并且其中调节器还包括一组辅助晶体管，串联连接在第二端 调节器的调节晶体管和输出端子，以及用于根据调节电压控制辅助晶体管的控制装置。
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公开(公告)号：US07027317B2
公开(公告)日：2006-04-11
申请号：US10720013
申请日：2003-11-20
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
CPC分类号： G11C11/005
摘要： A semiconductor memory comprises a plurality of memory cells, for example Flash memory cells, arranged in a plurality of lines, and a plurality of memory cell access signal lines, each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.
摘要翻译： 半导体存储器包括多个存储器单元，例如布置在多个行中的闪存单元，以及多个存储单元存取信号线，每个存储单元接入信号线与至少一个相应行的存储单元相关联，用于访问存储器 存储单元的至少一个相应行的单元; 每个信号线具有与其固有相关的电容。 提供了多个易失性存储单元，每个易失性存储单元具有电容存储元件。 每个易失性存储器单元与相应的信号线相关联，并且由与各个信号线固有相关联的电容形成的相应电容存储元件。 特别地，与存储器单元的矩阵的位线相关联的寄生电容可以被用作电容性存储元件。
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公开(公告)号：US06327184B1
公开(公告)日：2001-12-04
申请号：US09621019
申请日：2000-07-21
申请人： Rino Micheloni , Giovanni Campardo , Luca Crippa
发明人： Rino Micheloni , Giovanni Campardo , Luca Crippa
IPC分类号： G11C1606
CPC分类号： G11C16/28
摘要： The read circuit comprises an array branch having an input array node connected, via an array bit line, to an array cell; a reference branch having an input reference node connected, via a reference bit line, to a reference cell; a current-to-voltage converter connected to an output array node of the array branch and to an output reference node of the reference branch to supply on the output array node and the output reference node the respective electric potentials correlated to the currents flowing in the array memory cell and, respectively, in the reference memory cell; and a comparator connected at input to the output array node and output reference node and supplying as output a signal indicative of the contents stored in the array memory cell; and an array decoupling stage arranged between the input array node and the output array node to decouple the electric potentials of the input and output array nodes from one another.
摘要翻译： 读取电路包括具有通过阵列位线连接到阵列单元的输入阵列节点的阵列分支; 参考分支，其具有通过参考位线连接到参考单元的输入参考节点; 连接到阵列分支的输出阵列节点和参考分支的输出参考节点的电流 - 电压转换器，以在输出阵列节点和输出参考节点上提供与在 阵列存储单元，分别在参考存储单元中; 以及比较器，其输入端连接到所述输出阵列节点和输出参考节点，并且作为输出提供指示存储在所述阵列存储单元中的内容的信号; 以及布置在输入阵列节点和输出阵列节点之间的阵列解耦级，以将输入和输出阵列节点的电位彼此去耦。
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7.发明授权Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory 有权方法和相关电路，用于调整同步信号ATD的持续时间，用于定时访问非易失性存储器公开(公告)号：US06237104B1
公开(公告)日：2001-05-22
申请号：US09222070
申请日：1998-12-29
IPC分类号： G06F1200
摘要： A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.
摘要翻译： 讨论了用于调整集成在半导体上的电子存储器件中的存储器单元的读取阶段的脉冲同步信号的持续时间的方法和相关电路。 当脉冲同步信号检测到存储器单元的多个寻址输入端的至少一个输入端上的逻辑状态换向时，脉冲同步信号由脉冲发生器产生。 该方法产生由发生器产生的信号与具有预定持续时间的脉冲信号之间的逻辑和。 逻辑和用于启动读取阶段。
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公开(公告)号：US06181602B2
公开(公告)日：2001-01-30
申请号：US09322460
申请日：1999-05-28
IPC分类号： G11C1606
摘要： A method for reading memory cells that includes supplying simultaneously two memory cells, both storing a respective unknown charge condition; generating two electrical quantities, each correlated to a respective charge condition of the respective memory cell; comparing the two electrical quantities with each other; and generating a two-bit signal on the basis of the result of the comparison. A reading circuit includes a two-input comparator having two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter. Both the two-input comparator and the current/voltage converter comprise low threshold transistors.
摘要翻译： 一种用于读取存储单元的方法，包括同时提供两个存储相应未知充电条件的存储器单元; 产生两个电量，每个电量与相应存储器单元的相应充电条件相关; 将两个电量相互比较; 并根据比较结果产生2位信号。 读取电路包括并联的两个分支的双输入比较器，每个分支通过电流/电压转换器连接到相应的存储单元。 双输入比较器和电流/电压转换器均包括低阈值晶体管。
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公开(公告)号：US5923076A
公开(公告)日：1999-07-13
申请号：US811577
申请日：1997-03-05
IPC分类号： H01L23/485 , H01L29/78
CPC分类号： H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/12036 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： An integrated device having an N-type well region formed in a P-type substrate and an N.sup.+ type contact ring housed in the well region. The well region forms respective capacitors with a conductive layer superimposed on the substrate, and with the substrate itself. The conductive layer and the substrate are grounded, and the contact ring is connected to the supply, so that the two capacitors are in parallel to each other and, together with the internal resistance of the well region, form a filter for stabilizing the supply voltage. When connected to an input buffer stage of the device, the filter provides for damping the peaks produced on the supply line of the input buffer by high-current switching of the output buffers.
摘要翻译： 具有形成在P型衬底中的N型阱区和容纳在阱区中的N +型接触环的集成器件。 阱区形成具有叠加在衬底上的导电层以及衬底本身的各个电容器。 导电层和基板接地，接触环连接到电源，使得两个电容器彼此平行，并且与阱区域的内部电阻一起形成用于稳定电源电压的滤波器 。 当连接到器件的输入缓冲级时，滤波器通过输出缓冲器的高电流切换来提供阻尼输入缓冲器电源线上产生的峰值。
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10.发明授权Method for erasing non-volatile memory cells and corresponding memory device 有权擦除非易失性存储单元和相应存储器件的方法公开(公告)号：US07184319B2
公开(公告)日：2007-02-27
申请号：US10675221
申请日：2003-09-30
申请人： Rino Micheloni , Giovanni Campardo
发明人： Rino Micheloni , Giovanni Campardo
CPC分类号： G11C29/82 , G11C16/04 , G11C16/16 , G11C29/44 , G11C2029/1208
摘要： The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in array sectors, including at least one row decode circuit portion being supplied positive and negative voltages. The method is applied whenever the issue of the erase algorithm is negative, and comprises the following steps: forcing an incompletely erased sector into a read condition; scanning the rows of said sector to check for the possible presence of a spurious current indicating a fail state; identifying and electrically isolating the failed row; re-addressing from said failed row to a redundant row provided in the same sector; re-starting the erase algorithm.
摘要翻译： 本发明涉及一种用于擦除非易失性存储单元的方法，以及实现该方法的可编程和电可擦除类型的相应非易失性存储器件，并且包括以行和列布局组织的存储单元阵列， 并且被划分成阵列扇区，包括至少一个行解码电路部分被提供正和负电压。 每当擦除算法的问题为负时，该方法被应用，并且包括以下步骤：强制将未完全擦除的扇区进入读取状态; 扫描所述扇区的行以检查指示故障状态的寄生电流的可能存在; 识别和电隔离失败的行; 从所述故障行重新寻址到在同一扇区中提供的冗余行; 重新启动擦除算法。
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