公开(公告)号：US20090321826A1

公开(公告)日：2009-12-31

申请号：US12551999

申请日：2009-09-01

申请人： Giuseppe ARENA ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Giuseppe ARENA ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

摘要： A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.

摘要翻译： 用于实现高集成度功率MOS器件的方法包括以下步骤：提供具有第一类型导电性的掺杂半导体衬底; 在所述基板上形成具有较低导电率的半导体层; 在半导体层上形成厚度介于3000和13000A（埃）之间的介电层; 在电介质层上沉积硬掩模层; 通过掩模层掩蔽硬掩模层; 蚀刻硬掩模层和下面的介电层以限定多个硬掩模部分以保护所述介电层; 去除掩蔽层; 各向同性和横向蚀刻所述介电层，在所述硬掩模部分下面的所述介电层中形成横向空腔; 形成厚度为150至1500A（埃）的栅极氧化物，其在所述空腔中沉积导体材料并且在其上方，以形成与包括所述厚介电层和所述栅极氧化物的栅极结构完全对准的凹陷间隔物。

公开(公告)号：US20060138537A1

公开(公告)日：2006-06-29

申请号：US11285742

申请日：2005-11-21

申请人： Giuseppe Arena ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Giuseppe Arena ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

摘要： A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.

公开(公告)号：US08013384B2

公开(公告)日：2011-09-06

申请号：US12551999

申请日：2009-09-01

申请人： Giuseppe Arena ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Giuseppe Arena ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L21/00

CPC分类号： H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

摘要： A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.

摘要翻译： 用于实现高集成度功率MOS器件的方法包括以下步骤：提供具有第一类型导电性的掺杂半导体衬底; 在所述基板上形成具有较低导电率的半导体层; 在半导体层上形成厚度介于3000和13000A（埃）之间的介电层; 在电介质层上沉积硬掩模层; 通过掩模层掩蔽硬掩模层; 蚀刻硬掩模层和下面的介电层以限定多个硬掩模部分以保护所述介电层; 去除掩蔽层; 各向同性和横向蚀刻所述介电层，在所述硬掩模部分下面的所述介电层中形成横向空腔; 形成厚度为150至1500A（埃）的栅极氧化物，其在所述空腔中沉积导体材料并且在其上方，以形成与包括所述厚介电层和所述栅极氧化物的栅极结构完全对准的凹陷间隔物。

公开(公告)号：US07601610B2

公开(公告)日：2009-10-13

申请号：US11285742

申请日：2005-11-21

申请人： Giuseppe Arena ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Giuseppe Arena ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L21/20

CPC分类号： H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

摘要： A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.

摘要翻译： 用于实现高集成度功率MOS器件的方法包括以下步骤：提供具有第一类型导电性的掺杂半导体衬底; 在所述基板上形成具有较低导电率的半导体层; 在半导体层上形成厚度介于3000和13000A（埃）之间的介电层; 在电介质层上沉积硬掩模层; 通过掩模层掩蔽硬掩模层; 蚀刻硬掩模层和下面的介电层以限定多个硬掩模部分以保护所述介电层; 去除掩蔽层; 各向同性和横向蚀刻所述介电层，在所述硬掩模部分下面的所述介电层中形成横向空腔; 形成厚度为150至1500A（埃）的栅极氧化物，其在所述空腔中沉积导体材料并且在其上方，以形成与包括所述厚介电层和所述栅极氧化物的栅极结构完全对准的凹陷间隔物。

公开(公告)号：US20050139906A1

公开(公告)日：2005-06-30

申请号：US10749134

申请日：2003-12-30

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/94

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712

摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

摘要翻译： 具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。 栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。 第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

公开(公告)号：US07304335B2

公开(公告)日：2007-12-04

申请号：US11279967

申请日：2006-04-17

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L29/78 ,  H01L29/10

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712

摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

摘要翻译： 具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。 栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。 第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

公开(公告)号：US07067363B2

公开(公告)日：2006-06-27

申请号：US10749134

申请日：2003-12-30

申请人： Angelo Magri′ ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Angelo Magri′ ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L21/337 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712

摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

摘要翻译： 具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。 栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。 第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

公开(公告)号：US06506658B2

公开(公告)日：2003-01-14

申请号：US09752149

申请日：2000-12-29

申请人： Giuseppe D'Arrigo ,  Corrado Spinella ,  Salvatore Coffa ,  Giuseppe Arena ,  Marco Camalleri

发明人： Giuseppe D'Arrigo ,  Corrado Spinella ,  Salvatore Coffa ,  Giuseppe Arena ,  Marco Camalleri

IPC分类号： H01L21331

CPC分类号： H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

摘要： A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.

摘要翻译： 提供一种制造绝缘体上硅（SOI）晶片的方法，该方法包括其中埋有掺杂区的单晶硅衬底。 该方法包括形成从衬底的表面延伸到掺杂掩埋区的多个沟槽状开口，并且选择性地蚀刻穿过多个沟槽状开口以将掺杂掩埋区改变为多孔硅区。 多孔硅区域被氧化以获得用于SOI晶片的绝缘区域。