公开(公告)号：US20230268335A1

公开(公告)日：2023-08-24

申请号：US17679655

申请日：2022-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Juhan KIM ,  Sangmoon J. KIM ,  Mahbub RASHED ,  Navneet K. JAIN

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

公开(公告)号：US20210320650A1

公开(公告)日：2021-10-14

申请号：US16847807

申请日：2020-04-14

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uttam SAHA ,  Mahbub RASHED

IPC: H03K3/037 ,  H03K19/20

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a low clock load dynamic dual output latch circuit and methods of operation. The structure includes: a plurality of dynamic clocked stacks which are configured to receive input data and provide a true logical value and a complement logical value; and a plurality of holding stacks which are configured to provide a hold signal to the dynamic clocked stacks and output the true logical value and the complement logical value in response to the hold signal being activated.

公开(公告)号：US20230395675A1

公开(公告)日：2023-12-07

申请号：US17834053

申请日：2022-06-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. MAZZA ,  Jia ZENG ,  Xuelian ZHU ,  Mahbub RASHED ,  Neha NAYYAR ,  Collin A. TRANTER

IPC: H01L29/423

CPC classification number: H01L29/42376

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture. The structure includes a first contact connected in a cross couple circuit to at least two gate structures, and a second contact connected to the first contact at a location which is devoid of any via connection.

公开(公告)号：US20240304616A1

公开(公告)日：2024-09-12

申请号：US18118317

申请日：2023-03-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Xuelian ZHU ,  Navneet K. JAIN ,  Juhan KIM ,  James P. MAZZA ,  Jia ZENG ,  David C. PRITCHARD ,  Mahbub RASHED

IPC: H01L27/06 ,  H01Q1/38 ,  H01Q1/48

CPC classification number: H01L27/0617 ,  H01Q1/38 ,  H01Q1/48

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to antenna structures and methods of manufacture. The structure includes an antenna cell comprising a single P-well isolated by a deep trench isolation structure and including at least one diffusion region.

公开(公告)号：US20230335484A1

公开(公告)日：2023-10-19

申请号：US17723888

申请日：2022-04-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. MAZZA ,  Navneet K. JAIN ,  Xuelian ZHU ,  Jia ZENG ,  Mahbub RASHED

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/535 ,  H01L21/76898

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to local interconnect power rails merged with upper power rails and methods of manufacture. The structure includes: an active cell including contacts enclosed in active regions; at least one local interconnect power rail connecting to the contacts of the active regions; and at least one power rail above and connected to the at least one local interconnect power rail.