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    Methods of making a semiconductor memory device
    3.
    发明授权
    Methods of making a semiconductor memory device 有权
    制造半导体存储器件的方法

    公开(公告)号：US08446762B2

    公开(公告)日：2013-05-21

    申请号：US13071979

    申请日：2011-03-25

    申请人： Sanh D. Tang ,  Gordon A. Haller ,  Daniel H. Doyle

    发明人： Sanh D. Tang ,  Gordon A. Haller ,  Daniel H. Doyle

    IPC分类号： G11C11/34

    CPC分类号： H01L29/7841 ,  G11C11/401 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844

    摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

    摘要翻译： 单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。 通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子 他们在哪里举行。

    Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells
    4.
    发明授权
    Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells 有权
    形成场效应晶体管，多个场效应晶体管和包括多个单独存储单元的DRAM电路的方法

    公开(公告)号：US08222102B2

    公开(公告)日：2012-07-17

    申请号：US13070256

    申请日：2011-03-23

    申请人： Paul E. Grisham ,  Gordon A. Haller ,  Sanh D. Tang

    发明人： Paul E. Grisham ,  Gordon A. Haller ,  Sanh D. Tang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7851 ,  H01L21/76232 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66818 ,  H01L29/7854

    摘要： A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.

    摘要翻译： 形成场效应晶体管的方法包括在半导体衬底内形成沟槽隔离材料，并在沟道区的长度上在半导体材料沟道区的相对侧上形成沟道隔离材料。 沟槽隔离材料形成为包括沿着沟道长度部分地在沟道区域下方朝向彼此延伸的相对的绝缘突起，并且半导体材料被接收在突起上。 蚀刻沟槽隔离材料以沿着沟道长度露出半导体材料的相对侧。 半导体材料的暴露的相对侧沿通道长度被蚀刻以形成相对于突出部向上突出的通道翅片。 栅极沿着沟道长度形成在鳍的顶部和相对侧上。 公开了其它方法和结构。

    Methods of making a semiconductor memory device
    5.
    发明授权
    Methods of making a semiconductor memory device 有权
    制造半导体存储器件的方法

    公开(公告)号：US07944743B2

    公开(公告)日：2011-05-17

    申请号：US12537470

    申请日：2009-08-07

    申请人： Sanh D. Tang ,  Gordon A. Haller ,  Daniel H. Doyle

    发明人： Sanh D. Tang ,  Gordon A. Haller ,  Daniel H. Doyle

    IPC分类号： G11C11/34

    CPC分类号： H01L29/7841 ,  G11C11/401 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844

    摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

    摘要翻译： 单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。 通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子 他们在哪里举行。

    Memory Arrays and Methods of Fabricating Memory Arrays
    6.
    发明申请
    Memory Arrays and Methods of Fabricating Memory Arrays 有权
    内存数组和内存数组制作方法

    公开(公告)号：US20100273303A1

    公开(公告)日：2010-10-28

    申请号：US12828915

    申请日：2010-07-01

    申请人： Gordon A. Haller ,  Sanh D. Tang

    发明人： Gordon A. Haller ,  Sanh D. Tang

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/66621 ,  G11C11/405 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10891

    摘要： A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.

    摘要翻译： 存储器阵列包括形成在半导体衬底上的多个存储单元。 存储单元的个体包括分别包括栅极，沟道区和一对源极/漏极区的第一和第二场效应晶体管。 第一和第二场效应晶体管的栅极被硬连线在一起。 导电数据线硬连接到两个源极/漏极区域。 电荷存储装置硬连接到除二者之外的源极/漏极区域中的至少一个。 考虑了其他方面和实现方式，包括制造存储器阵列的方法。

    Transistor structures
    7.
    发明授权
    Transistor structures 有权
    晶体管结构

    公开(公告)号：US07659560B2

    公开(公告)日：2010-02-09

    申请号：US11716433

    申请日：2007-03-08

    申请人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    发明人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

    摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

    摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。

    Memory arrays and methods of fabricating memory arrays
    8.
    发明授权
    Memory arrays and methods of fabricating memory arrays 有权
    存储器阵列和制造存储器阵列的方法

    公开(公告)号：US08394699B2

    公开(公告)日：2013-03-12

    申请号：US12828915

    申请日：2010-07-01

    申请人： Gordon A. Haller ,  Sanh D. Tang

    发明人： Gordon A. Haller ,  Sanh D. Tang

    IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/66621 ,  G11C11/405 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10891

    摘要： A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.

    摘要翻译： 存储器阵列包括形成在半导体衬底上的多个存储单元。 存储单元的个体包括分别包括栅极，沟道区和一对源极/漏极区的第一和第二场效应晶体管。 第一和第二场效应晶体管的栅极被硬连线在一起。 导电数据线硬连接到两个源极/漏极区域。 电荷存储装置硬连接到除二者之外的源极/漏极区域中的至少一个。 考虑了其他方面和实现方式，包括制造存储器阵列的方法。

    Transistor Gate Forming Methods and Transistor Structures
    9.
    发明申请
    Transistor Gate Forming Methods and Transistor Structures 有权
    晶体管栅极形成方法和晶体管结构

    公开(公告)号：US20110092062A1

    公开(公告)日：2011-04-21

    申请号：US12977969

    申请日：2010-12-23

    申请人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    发明人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    IPC分类号： H01L21/28

    CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

    摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

    摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。