公开(公告)号：US06701426B1

公开(公告)日：2004-03-02

申请号：US09425037

申请日：1999-10-19

申请人： Greg L. Ries ,  Ronak S. Patel ,  Korbin S. Van Dyke ,  Niteen Patkar ,  T. R. Ramesh

发明人： Greg L. Ries ,  Ronak S. Patel ,  Korbin S. Van Dyke ,  Niteen Patkar ,  T. R. Ramesh

IPC分类号： G06F938

CPC分类号： G06F9/3806 ,  G06F9/30174 ,  G06F9/3848

摘要： A multiple instruction set processor and method dynamically activates one of a plurality of branch prediction processes depending upon which one of a multiple instruction set is operational. Shared branch history table structures are used and are indexed differently depending upon which instruction set is operational. The apparatus and method also allows switching between instruction set index generators for each of the plurality of instruction sets. Accordingly, different indexes to branch prediction data are used depending upon which of the plurality of instruction sets is operational. Shared memory may be used to contain branch prediction table data for instructions from each of the plurality of instruction sets in response to selection of an instruction set. Shared memory is also used to contain branch target buffer data for instructions from each of the plurality of instruction sets in response to selection of one of the instruction sets.

摘要翻译： 多指令集处理器和方法根据多指令集中的哪一个可操作地动态地激活多个分支预测处理中的一个。 使用共享分支历史表结构，并根据哪个指令集可操作而进行索引。 该装置和方法还允许在指令集索引生成器之间切换多个指令集中的每一个。 因此，取决于多个指令集中的哪一个是可操作的，使用不同的分支预测数据索引。 响应于指令集的选择，可以使用共享存储器来包含来自多个指令集中的每一个的指令的分支预测表数据。 响应于选择一个指令集，共享存储器还用于包含来自多个指令集中的每一个的指令的转移目标缓冲器数据。

公开(公告)号：US07069421B1

公开(公告)日：2006-06-27

申请号：US09429094

申请日：1999-10-28

申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh

发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh

IPC分类号： G06F9/30

CPC分类号： G06F9/45533

摘要： A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer. Interrupt circuitry is cooperatively designed with the instruction pipeline circuitry to trigger an interrupt on execution of an instruction of a process, synchronously based at least in part on a memory state of the computer and the address of the instruction, the architectural definition of the instruction not calling for an interrupt. A handler for the interrupt is responsive to the contents of the table to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the instruction.

摘要翻译： 微处理器芯片，以及用于该微处理器芯片的方法。 该芯片具有指令流水线电路和地址转换电路。 表查找电路索引到表中，该表具有与由地址转换电路翻译的每个相应地址范围相关联的条目。 该表的每个条目描述存在位于相应的相应地址范围内的指令的替代编码的可能性。 表查找电路检索对应于该地址的表条目，并可作为执行在计算机上执行的非主管模式程序的指令的基本指令周期的一部分。 中断电路与指令流水线电路协同设计，以至少部分地基于计算机的存储状态和指令的地址同步地触发执行过程指令的中断，指令的架构定义不是 要求中断。 用于中断的处理程序响应于表的内容，以影响指令流水线电路，以基于与该指令相关联的表条目的内容来实现对结构上可视数据操纵行为的控制或指令的控制传递行为。

公开(公告)号：US06826748B1

公开(公告)日：2004-11-30

申请号：US09339749

申请日：1999-06-24

申请人： Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

发明人： Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

IPC分类号： G06F944

CPC分类号： G06F9/45558 ,  G06F9/45541 ,  G06F9/45554 ,  G06F2009/45583

摘要： A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

摘要翻译： 用于执行该方法的方法和计算机。 在计算机上执行程序时，计算机使用通用寄存器文件的寄存器来存储指令结果。 描述可概要事件的简档信息可记录在通用寄存器文件中，因为可以描述事件的发生，而无需先将信息捕获到计算机的主存储器中。

公开(公告)号：US20090204785A1

公开(公告)日：2009-08-13

申请号：US11982419

申请日：2007-10-31

申请人： John S. Yates, JR. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

发明人： John S. Yates, JR. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

IPC分类号： G06F9/30 ,  G06F12/10

CPC分类号： G06F9/30189 ,  G06F9/30174 ,  G06F9/30196 ,  G06F9/3802

摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线识别来自第一页面的执行流程，其相关联的指示符元素指示第一架构。 或执行约定，到第二页，其相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。

公开(公告)号：US07013456B1

公开(公告)日：2006-03-14

申请号：US09334530

申请日：1999-06-16

申请人： Korbin S. Van Dyke ,  Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Stephen C. Purcell ,  Niteen Aravind Patkar

发明人： Korbin S. Van Dyke ,  Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Stephen C. Purcell ,  Niteen Aravind Patkar

IPC分类号： G06F9/44

CPC分类号： G06F9/45533 ,  G06F9/45541 ,  G06F9/45554

摘要： A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.

摘要翻译： 一种用于执行该方法的方法和计算机。 在计算机上执行程序时，检测到在指令流水线中发生的可轮廓事件。 该指令流水线用于记录描述可概要事件的简档信息，基本上与可概要事件的发生同时发生。 检测和记录在没有软件干预的情况下在计算机硬件的控制下进行。

公开(公告)号：US06654872B1

公开(公告)日：2003-11-25

申请号：US09490888

申请日：2000-01-27

申请人： T. R. Ramesh ,  Korbin S. Van Dyke

发明人： T. R. Ramesh ,  Korbin S. Van Dyke

IPC分类号： G06F9315

CPC分类号： G06F9/3816 ,  G06F9/30149

摘要： An instruction aligner and method evaluates a fixed length instruction cache line by breaking it into at least two components. These two components, in one embodiment, include half of the instruction cache line being designated as most significant bytes and the second half of the instruction cache line being designated as least significant bytes. A byte right rotator is responsible for feeding the next sixteen bytes of the instruction stream, while a byte right shifter shifts the unused bytes of the current sixteen bytes the aligner is working on. The byte rotator and byte shifter combine to provide aligned variable length instructions for decoding based on either a fetch PC value or current instruction length.

摘要翻译： 指令对齐器和方法通过将固定长度的指令高速缓存行分解成至少两个组件来评估它。 在一个实施例中，这两个组件包括指定高速缓存行的一半被指定为最高有效字节，指令高速缓存行的后半部分被指定为最低有效字节。 一个字节右旋转器负责馈送指令流的下一个十六个字节，而一个字节右移位器移位对准器正在工作的当前十六个字节的未使用字节。 字节转换器和字节移位器组合以提供对准的可变长度指令，用于基于获取的PC值或当前指令长度进行解码。

公开(公告)号：US07941647B2

公开(公告)日：2011-05-10

申请号：US11982419

申请日：2007-10-31

申请人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

发明人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

IPC分类号： G06F9/22

CPC分类号： G06F9/30189 ,  G06F9/30174 ,  G06F9/30196 ,  G06F9/3802

摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线将来自第一页面的执行流程（其相关联的指示符元素指示第一架构或执行约定）识别到第二页面，其第二页面的相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。

公开(公告)号：US06941545B1

公开(公告)日：2005-09-06

申请号：US09322443

申请日：1999-05-28

申请人： David L. Reese ,  John S. Yates, Jr. ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

发明人： David L. Reese ,  John S. Yates, Jr. ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

IPC分类号： G06F9/455 ,  G06F9/44

CPC分类号： G06F9/45554 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45583

摘要： A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.

摘要翻译： 一台电脑。 指令流水线和存储器访问单元在计算机的存储器的逻辑地址空间中执行指令。 地址转换电路将由程序生成的地址参考从程序的逻辑地址空间转换为计算机的物理地址空间。 简档电路与指令流水线协作地互连，并且被配置为在没有编译器帮助执行分析的情况下检测在指令流水线中发生的可概要事件的发生，并且与存储器访问单元协作地互连以记录描述参考的物理存储器地址的简档信息 程序的执行间隔。

公开(公告)号：US06934832B1

公开(公告)日：2005-08-23

申请号：US09667226

申请日：2000-09-21

申请人： Korbin S. Van Dyke ,  Paul Campbell ,  Shalesh Thusoo ,  T. R. Ramesh ,  Alan McNaughton

发明人： Korbin S. Van Dyke ,  Paul Campbell ,  Shalesh Thusoo ,  T. R. Ramesh ,  Alan McNaughton

IPC分类号： G06F11/00

CPC分类号： G06F9/30174 ,  G06F9/3851 ,  G06F9/3861

摘要： A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, (b) for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline; (c) to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer; and (d) to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete. The pipeline exception circuitry is designed to recognize an exception occurring in an instruction after a first side-effect of the instruction has been architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler. Pipeline resumption circuitry is effective, after completion of the software exception handler, to resume execution of the excepted program based on the information in the processor registers. The processor registers of the computer are designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory, the processor registers and general purpose registers of the computer together providing sufficient working storage for execution of the exception handler and resumption of the program, without storing processor state to the main memory.

公开(公告)号：US08788792B2

公开(公告)日：2014-07-22

申请号：US13371766

申请日：2012-02-13

申请人： John S. Yates, Jr. ,  Matthew F. Storch ,  Sandeep Nijhawan ,  Dale R. Jurich ,  Korbin S. Van Dyke

发明人： John S. Yates, Jr. ,  Matthew F. Storch ,  Sandeep Nijhawan ,  Dale R. Jurich ,  Korbin S. Van Dyke

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/45554 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3861

摘要： A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.

摘要翻译： 多指令集架构（ISA）计算机系统包括计算机程序，第一处理器，第二处理器，轮廓仪和翻译器。 计算机程序包括第一ISA的指令，第一ISA具有第一复杂度。 第一处理器被配置为执行第一ISA的指令。 第二处理器被配置为执行第二ISA的指令，第二ISA不同于第一ISA并且具有第二复杂度，其中第二复杂度小于第一复杂度。 分析器被配置为选择用于转换为第二ISA的指令的计算机程序的块，其中该块包括第一ISA的一个或多个指令。 翻译器被配置为将第一ISA的块转换为第二ISA的指令以供第二处理器执行。