公开(公告)号：US5659796A

公开(公告)日：1997-08-19

申请号：US422072

申请日：1995-04-13

申请人： Gregory M. Thorson ,  Steven L. Scott

发明人： Gregory M. Thorson ,  Steven L. Scott

IPC分类号： H04L12/56 ,  G06F13/00 ,  G06F13/12

CPC分类号： H04L45/12 ,  H04L45/10

摘要： A method optimizes routing in a multiprocessor computer system by defining two types of virtual channels having virtual channel buffers for storing messages communicated between processing element nodes in the multiprocessor computer system. A dateline is associated to each type of virtual channel, and messages are restrained from crossing a dateline on its associated type of virtual channel to avoid deadlock. A cost function is defined which is correlated to imbalances in the utilization of the two types of virtual channels. The unrestrained messages are allocated between the two types of virtual channels to minimize the cost function by defining an initial virtual channel allocation, randomly modifying the virtual channel allocation, and accepting the random modification if the modification decreases the cost function, else accepting the modification based on a probability that slowly decreases during the allocating step.

摘要翻译： 一种方法通过定义具有用于存储在多处理器计算机系统中的处理元件节点之间传送的消息的虚拟通道缓冲器的两种类型的虚拟通道来优化多处理器计算机系统中的路由。 数据线与每种类型的虚拟通道相关联，并且阻止消息跨越其相关联的虚拟通道类型的数据线以避免死锁。 定义了与两种虚拟通​​道的使用中的不平衡相关的成本函数。 在两种类型的虚拟信道之间分配无限制的消息以通过定义初始虚拟信道分配，随机修改虚拟信道分配来最小化成本函数，并且如果修改降低成本函数则接受随机修改，否则接受基于修改的修改 在分配步骤中缓慢降低的概率。

公开(公告)号：US5701416A

公开(公告)日：1997-12-23

申请号：US421566

申请日：1995-04-13

申请人： Gregory M. Thorson ,  Steven L. Scott

发明人： Gregory M. Thorson ,  Steven L. Scott

IPC分类号： G06F15/173 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F15/17331 ,  G06F15/17381

摘要： A routing mechanism includes two acyclic non-adaptive virtual channels having two types of virtual channel buffers to store packets along deterministic virtual paths between nodes in an n-dimensional networked system, and an adaptive virtual channel having a third type of virtual channel buffer to store the packets along non-deterministic virtual paths between the nodes. The packets are routed between the nodes along either selected portions of the deterministic virtual paths or selected portions of the non-deterministic virtual paths based on routing information such that a packet is never routed on a selected portion of one of the non-deterministic virtual paths unless the third type virtual channel buffer associated with the selected portion of the one non-deterministic virtual path has sufficient space available to store the entire packet.

摘要翻译： 路由机制包括两个非循环非自适应虚拟信道，其具有两种类型的虚拟信道缓冲器，用于沿着n维网络系统中的节点之间的确定性虚拟路径存储分组，以及具有第三类型虚拟信道缓冲器以存储的自适应虚拟信道 节点之间的非确定性虚拟路径的数据包。 基于路由信息，分组沿着确定性虚拟路径的所选部分或非确定性虚拟路径的选定部分在节点之间路由，使得分组绝不在非确定性虚拟路径之一的所选部分上路由 除非与所述一个非确定性虚拟路径的选定部分相关联的第三类型虚拟通道缓冲器具有足够的可用于存储整个分组的空间。

公开(公告)号：US08036247B2

公开(公告)日：2011-10-11

申请号：US11620215

申请日：2007-01-05

申请人： Paul R. Frank ,  Gregory M. Thorson ,  Russell L. Nicol ,  Donglai Dai ,  Joseph M. Placek

发明人： Paul R. Frank ,  Gregory M. Thorson ,  Russell L. Nicol ,  Donglai Dai ,  Joseph M. Placek

IPC分类号： H04J3/06

CPC分类号： G06F1/12 ,  G06F1/14

摘要： A system and method of determining a master node in a computer system having a plurality of nodes includes establishing a hierarchy of master nodes from the plurality of nodes, wherein the master node synchronizes the plurality of nodes in the computer system with a clock value and determining the master node from the hierarchy of master nodes. A system and method of synchronizing a plurality of nodes in a computer system includes determining a master node from the plurality of nodes, sending a clock value from the master node to neighbor nodes of the master node, synchronizing a node clock in each node receiving the clock value if a predetermined period of time has elapsed in each receiving node, distributing a node clock value from each synchronized node to neighbor nodes of the synchronized node, and repeating synchronizing and distributing, wherein synchronizing a node clock in each node receiving the clock value includes each node receiving the node clock value.

摘要翻译： 一种确定具有多个节点的计算机系统中的主节点的系统和方法包括从所述多个节点建立主节点的层级，其中所述主节点将所述计算机系统中的所述多个节点与时钟值同步并确定 主节点从主节点的层次结构。 在计算机系统中同步多个节点的系统和方法包括从多个节点确定主节点，从主节点向主节点的邻居节点发送时钟值，使得接收到节点的每个节点中的节点时钟同步 在每个接收节点中经过预定时间段的时钟值，将来自每个同步节点的节点时钟值分配给同步节点的相邻节点，并且重复同步和分配，其中，同步接收时钟值的每个节点中的节点时钟 包括接收节点时钟值的每个节点。

公开(公告)号：US20090259696A1

公开(公告)日：2009-10-15

申请号：US12330413

申请日：2008-12-08

申请人： John Carter ,  Randal S. Passint ,  Donglai Dai ,  Zhen Fang ,  Lixin Zhang ,  Gregory M. Thorson

发明人： John Carter ,  Randal S. Passint ,  Donglai Dai ,  Zhen Fang ,  Lixin Zhang ,  Gregory M. Thorson

IPC分类号： G06F17/30

CPC分类号： G06F15/16 ,  Y10S707/99952

摘要： A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.

摘要翻译： 用于控制一组访问节点对家庭节点（在多模式计算机系统中）的存储器的访问的方法和装置确定该组节点中的每个节点已经访问了存储器，并将完成消息转发到 在确定每个节点已访问存储器之后，节点集合。 完成消息具有指示节点集合中的每个节点已经访问了家庭节点的存储器的数据。

公开(公告)号：US06643764B1

公开(公告)日：2003-11-04

申请号：US09620372

申请日：2000-07-20

申请人： Gregory M. Thorson ,  Steven Scott ,  Ram Gupta ,  William A. Huffman

发明人： Gregory M. Thorson ,  Steven Scott ,  Ram Gupta ,  William A. Huffman

IPC分类号： G06F15163

CPC分类号： H04L45/302 ,  H04L45/00 ,  H04L45/22 ,  H04L45/742

摘要： A multiprocessor computer system comprises a plurality of processing element nodes and an interconnect network interconnecting the plurality of processing element nodes. An interface circuit is associated with each one of the plurality of processing element nodes. The interface circuit has a lookup table having n-number of routing entries for a given destination node. Each one of the n-number of routing entries associated with a different class of traffic. The network traffic is routed according to the class.

摘要翻译： 多处理器计算机系统包括多个处理单元节点和互连多个处理单元节点的互连网络。 接口电路与多个处理元件节点中的每一个相关联。 接口电路具有用于给定目的地节点的具有n个路由条目的查找表。 与不同类别的流量相关联的n个路由条目中的每一个。 网络流量根据类进行路由。

公开(公告)号：US06578115B2

公开(公告)日：2003-06-10

申请号：US10047347

申请日：2002-01-14

申请人： David E. McCracken ,  Martin M. Deneroff ,  Gregory M. Thorson ,  John S. Keen

发明人： David E. McCracken ,  Martin M. Deneroff ,  Gregory M. Thorson ,  John S. Keen

IPC分类号： G06F1208

CPC分类号： G06F11/2051 ,  G06F12/0808 ,  G06F12/0817

摘要： A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and identities of processors (16) affected by the invalidation request to the local block unit (28). The local block unit (28) determines which ones of the identified processors (16) are present in the computer system (10) and generates an invalidation message for each present processor (16) for transfer thereto. Each of the present processors (16) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit (24) that generated the invalidation request. The local block unit (28) determines which ones of the identified processors (16) are not present in the computer system (10) and generates an acknowledgment message for each non-existent processor (16). Each acknowledgment message is transferred to the processor interface unit (24) which generated the invalidation request.

公开(公告)号：US06339812B1

公开(公告)日：2002-01-15

申请号：US09410139

申请日：1999-09-30

申请人： David E. McCracken ,  Martin M. Deneroff ,  Gregory M. Thorson ,  John S. Keen

发明人： David E. McCracken ,  Martin M. Deneroff ,  Gregory M. Thorson ,  John S. Keen

IPC分类号： G06F1208

CPC分类号： G06F11/2051 ,  G06F12/0808 ,  G06F12/0817

摘要： A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and identities of processors (16) affected by the invalidation request to the local block unit (28). The local block unit (28) determines which ones of the identified processors (16) are present in the computer system (10) and generates an invalidation message for each present processor (16) for transfer thereto. Each of the present processors (16) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit (24) that generated the invalidation request. The local block unit (28) determines which ones of the identified processors (16) are not present in the computer system (10) and generates an acknowledgment message for each non-existent processor (16). Each acknowledgment message is transferred to the processor interface unit (24) which generated the invalidation request.

摘要翻译： 计算机系统（10）中的节点控制器（12）包括处理器接口单元（24），存储器目录接口单元（22）和局部块单元（28）。 响应于与存储器目录接口单元（22）相关联的存储器（17）中的存储器位置被改变，处理器接口单元（24）生成用于传送到存储器目录接口单元（22）的无效请求。 存储器目录接口单元（22）将无效请求和无效请求影响的处理器（16）的标识提供给本地块单元（28）。 本地块单元（28）确定在计算机系统（10）中存在哪个已识别的处理器（16），并为每个当前处理器（16）生成用于传送的无效消息。 本处理器（16）中的每一个处理它们的无效消息，并产生用于传送到产生无效请求的处理器接口单元（24）的确认消息。 本地块单元（28）确定在计算机系统（10）中哪个识别的处理器（16）不存在，并为每个不存在的处理器（16）生成确认消息。 每个确认消息被传送到产生无效请求的处理器接口单元（24）。

公开(公告)号：US20130246653A1

公开(公告)日：2013-09-19

申请号：US13873058

申请日：2013-04-29

申请人： Martin M. Deneroff ,  Gregory M. Thorson ,  Randal S. Passint

发明人： Martin M. Deneroff ,  Gregory M. Thorson ,  Randal S. Passint

IPC分类号： G06F15/173

CPC分类号： G06F15/17312 ,  G06F15/17343 ,  G06F15/17381 ,  H04L45/14 ,  H04L67/1002

摘要： A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

公开(公告)号：US20090222821A1

公开(公告)日：2009-09-03

申请号：US12039048

申请日：2008-02-28

申请人： Eric C. Fromm ,  Gregory M. Thorson

发明人： Eric C. Fromm ,  Gregory M. Thorson

IPC分类号： G06F9/50

CPC分类号： G06F9/5016 ,  G06F2209/5021

摘要： Processing transaction requests in a shared memory multi-processor computer network is described. A transaction request is received at a servicing agent from a requesting agent. The transaction request includes a request priority associated with a transaction urgency generated by the requesting agent. The servicing agent provides an assigned priority to the transaction request based on the request priority, and then compares the assigned priority to an existing service level at the servicing agent to determine whether to complete or reject the transaction request. A reply message from the servicing agent to the requesting agent is generated to indicate whether the transaction request was completed or rejected, and to provide reply fairness state data for rejected transaction requests.

摘要翻译： 描述在共享存储器多处理器计算机网络中处理事务请求。 在请求代理处的服务代理处接收到交易请求。 交易请求包括与请求代理产生的事务紧急性相关联的请求优先级。 服务代理根据请求优先级为交易请求提供分配的优先级，然后将分配的优先级与服务代理处的现有服务级别进行比较，以确定是否完成或拒绝交易请求。 产生从服务代理到请求代理的回复消息，以指示交易请求是否已完成或拒绝，并为拒绝的交易请求提供回复公平状态数据。

公开(公告)号：US06973559B1

公开(公告)日：2005-12-06

申请号：US09408972

申请日：1999-09-29

申请人： Martin M. Deneroff ,  Gregory M. Thorson ,  Randal S. Passint

发明人： Martin M. Deneroff ,  Gregory M. Thorson ,  Randal S. Passint

IPC分类号： G06F15/16 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F15/17312 ,  G06F15/17343 ,  G06F15/17381 ,  H04L45/14 ,  H04L67/1002

摘要： A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

摘要翻译： 提供了一种用于在可扩展多处理器系统内互连多个处理元件节点的系统和方法。 每个处理元件节点包括至少一个处理器和存储器。 可扩展互连网络包括互连集群中的处理元件节点的物理通信链路。 可伸缩互连网络中的第一组路由器在多个处理单元节点之间路由消息。 可扩展互连网络中的一个或多个元变换器在第一组路由器之间路由消息，使得第一集群中的每个路由器通过一个或多个元变换器连接到所有其他集群。