公开(公告)号：US07213126B1

公开(公告)日：2007-05-01

申请号：US10755742

申请日：2004-01-12

申请人： Gregory William Smaus ,  Raghuram S. Tupuri ,  Gerald D. Zuraski, Jr.

发明人： Gregory William Smaus ,  Raghuram S. Tupuri ,  Gerald D. Zuraski, Jr.

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/382 ,  G06F12/0875

摘要： A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be associated with a respective address. The trace cache memory is coupled to the trace generator and includes a plurality of entries each configured to store one of the traces. The trace generator may be further configured to restrict each of the traces to include only operations having respective addresses that fall within one or more predetermined ranges of contiguous addresses.

摘要翻译： 处理器包括耦合到跟踪发生器的跟踪高速缓冲存储器。 跟踪发生器可以被配置为生成多个迹线，每个迹线包括可以从一个或多个指令解码的一个或多个操作。 每个操作可以与相应的地址相关联。 跟踪高速缓存存储器耦合到跟踪生成器，并且包括多个条目，每个条目被配置为存储跟踪的一个。 跟踪发生器还可以被配置为限制每个迹线仅包括具有落在连续地址的一个或多个预定范围内的相应地址的操作。

公开(公告)号：US06259637B1

公开(公告)日：2001-07-10

申请号：US09728285

申请日：2000-12-01

申请人： Timothy J. Wood ,  Raghuram S. Tupuri ,  Gerald D. Zuraski, Jr.

发明人： Timothy J. Wood ,  Raghuram S. Tupuri ,  Gerald D. Zuraski, Jr.

IPC分类号： G11C700

CPC分类号： G11C29/4401 ,  G11C29/44

摘要： An integrated circuit device includes a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns. First and second redundant rows of memory cells and a first redundant column of memory cells are provided. A test circuit is coupled to the memory array and is adapted to test a plurality of memory cells coupled to each of the plurality of rows. A control circuit is coupled to the test circuit and is adapted to receive test results from the test circuit, the control circuit being adapted to respond to a detection of a defective memory cell to determine an assignment of at least one of the first and second redundant rows and first redundant column. A first register is coupled to the control circuit and adapted to receive an assignment of the first redundant row in response to a determination by the control circuit, a second register is coupled to the control circuit and adapted to receive an assignment of the first redundant column in response to a determination by the control circuit, and a third register is coupled to the control circuit and adapted to receive an assignment of the second redundant row in response to a determination by the control circuit.

摘要翻译： 集成电路装置包括具有以多行和多列布置的多个存储单元的存储器阵列。 提供存储单元的第一和第二冗余行和存储器单元的第一冗余列。 测试电路耦合到存储器阵列，并且适于测试耦合到多个行中的每一行的多个存储器单元。 控制电路耦合到测试电路并且适于从测试电路接收测试结果，所述控制电路适于响应于有缺陷的存储器单元的检测，以确定第一和第二冗余中的至少一个的分配 行和第一冗余列。 第一寄存器耦合到控制电路并且适于响应于控制电路的确定而接收第一冗余行的分配，第二寄存器耦合到控制电路并且适于接收第一冗余列的分配 响应于控制电路的确定，并且第三寄存器耦合到控制电路，并且适于响应于控制电路的确定而接收第二冗余行的分配。

公开(公告)号：US06560740B1

公开(公告)日：2003-05-06

申请号：US09366444

申请日：1999-08-03

申请人： Gerald D. Zuraski, Jr. ,  Timothy J. Wood ,  Raghuram S. Tupuri

发明人： Gerald D. Zuraski, Jr. ,  Timothy J. Wood ,  Raghuram S. Tupuri

IPC分类号： G01R3128

CPC分类号： G11C29/36 ,  G01R31/3187 ,  G11C29/16 ,  G11C29/846 ,  G11C2029/3202 ,  G11C2207/104

摘要： An apparatus and method are presented for programmable built-in self-test (BIST) and built-in self-repair (BISR) of an embedded memory (i.e., a memory formed with random logic upon a semiconductor substrate). A semiconductor device may include a memory unit, a BIST logic unit coupled to the memory unit, and a master test unit coupled to the BIST logic unit and the memory unit. The memory unit stores data input signals in response to a first set of address and control signals, and provides the stored data input signals as data output signals in response to a second set of address and control signals. The master test unit provides the memory test pattern to the BIST logic unit and generates the first and second sets of address and control signals. The BIST logic unit stores the memory test pattern, produces the data input signals dependent upon the memory test pattern, provides the data input signals to the memory unit, receives the data output signals from the memory unit, and compares the data output signals to the data input signals to form BIST results. The BIST system may perform a hardwired BIST routine when an asserted RESET signal is received by the semiconductor device and/or a programmable BIST routine under software control. The BIST logic unit may include a redundant memory structure, and may be configured to functionally replace a defective memory structure of the memory unit with one of the redundant memory structures dependent upon the BIST results.

摘要翻译： 提出了一种用于嵌入式存储器（即，在半导体衬底上形成有随机逻辑的存储器）的可编程内置自检（BIST）和内置自修复（BISR）的装置和方法。 半导体器件可以包括存储器单元，耦合到存储器单元的BIST逻辑单元和耦合到BIST逻辑单元和存储器单元的主测试单元。 存储单元响应于第一组地址和控制信号存储数据输入信号，并且响应于第二组地址和控制信号将存储的数据输入信号提供为数据输出信号。 主测试单元向BIST逻辑单元提供存储器测试模式，并产生第一组和第二组地址和控制信号。 BIST逻辑单元存储存储器测试模式，产生取决于存储器测试模式的数据输入信号，将数据输入信号提供给存储器单元，从存储器单元接收数据输出信号，并将数据输出信号与 数据输入信号形成BIST结果。 当由半导体器件接收到断言的RESET信号和/或软件控制下的可编程BIST例程时，BIST系统可以执行硬连线BIST程序。 BIST逻辑单元可以包括冗余存储器结构，并且可以被配置为使用依赖于BIST结果的冗余存储器结构之一来功能地替换存储器单元的有缺陷的存储器结构。

公开(公告)号：US06502188B1

公开(公告)日：2002-12-31

申请号：US09441630

申请日：1999-11-16

申请人： Gerald D. Zuraski, Jr. ,  James S. Roberts ,  Raghuram S. Tupuri

发明人： Gerald D. Zuraski, Jr. ,  James S. Roberts ,  Raghuram S. Tupuri

IPC分类号： G06F940

CPC分类号： G06F9/3806 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3848 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/4486

摘要： A branch prediction unit includes a local branch prediction and a global branch prediction. A global branch prediction utilizes a global history shift register to record the behavior of conditional branches. In some cases, a conditional branch may behave in a static manner, either always being taken or not taken, while resident in an instruction cache. Such static behaving conditional branches do not need a global history for prediction and contend with other conditional branches for global branch history training. By utilizing a dynamic branch classification scheme, branches requiring global history prediction can be identified and static behaving conditional branches may be prevented from polluting the global history. All conditional branches are initially classified as local and do not participate in global history training. Only after two mispredictions are branches recognized as exhibiting dynamic behavior and classified as global. These branches classified as global may then participate in global history training and utilize a global history based branch prediction.

摘要翻译： 分支预测单元包括本地分支预测和全局分支预测。 全局分支预测利用全局历史移位寄存器来记录条件分支的行为。 在某些情况下，条件分支可以以静态方式表现，或者始终被采取或不占用，而驻留在指令高速缓存中。 这种静态行为条件分支不需要全球预测历史，并与其他条件分支进行全球分支历史训练。 通过使用动态分支分类方案，可以识别需要全局历史预测的分支，并且可以防止静态行为条件分支污染全球历史。 所有有条件的分支最初被分类为地方，不参加全球历史训练。 只有经过两次误解，分支机构被认为是表现出动态行为，被列为全球性的。 这些分类为全球的分支可以参与全球历史培训，并利用全球历史分支预测。

公开(公告)号：US06208543B1

公开(公告)日：2001-03-27

申请号：US09314064

申请日：1999-05-18

申请人： Raghuram S. Tupuri ,  Greg A. Constant

发明人： Raghuram S. Tupuri ,  Greg A. Constant

IPC分类号： G11C1500

CPC分类号： G11C15/00

摘要： A memory unit is presented including a data array for storing data items (e.g., instructions and/or data) a hit circuit, and a miss circuit. The data items stored within the data array are accessed by multiple data access signals, wherein assertion of one of the data access signals indicates the presence of a requested data item within the data array. The hit circuit includes multiple driver cells coupled to two signal lines: a bit line and a bit′ line. Each driver cell receives a different one of the data access signals. When one of the data access signals is asserted, the receiving driver cell drives the bit line toward a first voltage level (e.g., VCC), and drives the bit′ line toward a second voltage level (e.g., VSS). The miss circuit is coupled to the bit and bit′ lines, and drives the bit line toward VSS. The strength with which the miss circuit drives the bit line toward VSS is less than the strength with which the hit circuit drives the bit line toward VCC such that a differential voltage is quickly and reliably developed between the bit and bit′ lines which indicates the presence or absence of the requested data item within the data array. A translation lookaside buffer (TLB) implementation of the memory unit is described, as is a cache unit including the TLB implementation, a processor including the cache unit, and a computer system including the processor.

摘要翻译： 提出了一种存储单元，其包括用于存储命中电路的数据项（例如指令和/或数据）的数据阵列和未命中电路。 存储在数据阵列内的数据项由多个数据访问信号访问，其中一个数据访问信号的断言指示数据阵列内存在所请求的数据项。 命中电路包括耦合到两个信号线的多个驱动器单元：位线和位线。 每个驱动器单元接收不同的数据访问信号。 当数据访问信号之一被断言时，接收驱动单元将位线驱动到第一电压电平（例如，VCC），并将位线驱动到第二电压电平（例如，VSS）。 漏电路耦合到位和位线，并将位线驱动到VSS。 漏电路驱动位线到VSS的强度小于命中电路驱动位线到VCC的强度，使得在位和位线之间快速可靠地产生差分电压，这表明存在 或数据数组中没有所请求的数据项。 描述存储器单元的翻译后备缓冲器（TLB）实现，以及包括TLB实现的缓存单元，包括高速缓存单元的处理器以及包括处理器的计算机系统。

公开(公告)号：US5892373A

公开(公告)日：1999-04-06

申请号：US790393

申请日：1997-01-29

申请人： Raghuram S. Tupuri ,  Stephen C. Horne

发明人： Raghuram S. Tupuri ,  Stephen C. Horne

IPC分类号： H03K3/037 ,  H03K19/096

CPC分类号： H03K3/0375

摘要： A gated clock driver is configured to provide an enable signal and a gated clock signal at each of a plurality flip-flops. One of the p-channel transistors of the gated clock driver's NOR gate is distributed to each of the flip-flops or latches in the system. Additionally, an extra n-channel transistor is provided in the gated clock circuit to form an inverter with the nondistributed p-channel transistor. More particularly, the p-channel transistor that is driven by the system clock input is distributed to each of the flip-flops. Similarly, the enable input (at the output of the new inverter) is distributed to each of the flip-flops. Since the gated clock signal cannot be generated without the enable signal being high and the system clock being low, distributing enable and the p-channel transistor which receives the system clock as an input minimizes clock skew as compared to flip-flops with a completely shared clock gating clock.

摘要翻译： 门控时钟驱动器被配置为在多个触发器中的每一个提供使能信号和门控时钟信号。 门控时钟驱动器的或非门的p沟道晶体管之一被分配到系统中的每个触发器或锁存器。 此外，在门控时钟电路中提供了额外的n沟道晶体管，以形成具有非分布式p沟道晶体管的反相器。 更具体地，由系统时钟输入驱动的p沟道晶体管被分配到每个触发器。 类似地，使能输入（在新的反相器的输出处）被分配给每个触发器。 由于门控时钟信号不能在没有使能信号为高电平且系统时钟为低的情况下产生，所以与具有完全共享的触发器相比，接收系统时钟作为输入的分配使能和p沟道晶体管使时钟偏移最小化 时钟门控时钟。

公开(公告)号：US5617431A

公开(公告)日：1997-04-01

申请号：US284163

申请日：1994-08-02

申请人： Raghuram S. Tupuri ,  Harikumar B. Nair

发明人： Raghuram S. Tupuri ,  Harikumar B. Nair

IPC分类号： G01R31/3183 ,  G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/318392 ,  G01R31/318307 ,  G01R31/318544 ,  G01R31/318505

摘要： Test vectors are applied to a single integrated circuit containing at least one logic core for which a preexisting test vector set exists. Each test vector ordinarily applied in one cycle to test a core by itself, is converted into a first and second test vector. The first test vector is applied to input pins of the single integrated circuit during a first time period. Test registers connected to the input pins of the integrated circuit are loaded with signal values from the first test vector. The test registers are loaded according to a load signal. The test registers are connected between the input pins and a first set of drivers, the drivers being connected to the logic core under test. The second test vector is applied through the input pins to a second set of drivers during a second time period. A test mode signal is provided from a test interface to control the drivers. The signals stored in the test registers are provided concurrently with the signals applied to the input pins of the integrated circuit during the second time period to the logic core under test through the first and second drivers respectively.

摘要翻译： 将测试向量应用于包含至少一个存在预先存在的测试向量集的逻辑核心的单个集成电路。 通常在一个周期中施加的每个测试矢量本身测试一个核心，被转换成第一和第二测试向量。 第一个测试向量在第一个时间周期内被应用于单个集成电路的输入引脚。 连接到集成电路的输入引脚的测试寄存器加载有来自第一个测试向量的信号值。 测试寄存器根据负载信号进行加载。 测试寄存器连接在输入引脚和第一组驱动器之间，驱动器连接到待测逻辑内核。 在第二时间段期间，通过输入引脚将第二测试矢量施加到第二组驱动器。 从测试接口提供测试模式信号以控制驱动器。 存储在测试寄存器中的信号分别与通过第一和第二驱动器分别在第二时间段期间施加到被测逻辑核心的集成电路的输入引脚的信号同时提供。

公开(公告)号：US5420818A

公开(公告)日：1995-05-30

申请号：US176671

申请日：1994-01-03

申请人： Frank J. Svejda ,  Raghuram S. Tupuri

发明人： Frank J. Svejda ,  Raghuram S. Tupuri

IPC分类号： G11C17/12 ,  H03K19/177 ,  G11C17/00 ,  G11C11/40

CPC分类号： G11C17/12 ,  H03K19/17704

摘要： A static read-only-memory (ROM) is derived from a gate array in which both P-channel transistor (24) and an N-channel transistor (30) are used to convey a logic 1 or 0 to a bitline (Bitline0). The invention maximizes the use of gate array transistors in a gate-array chip and achieves a high density of ROM bits per unit area. In CMOS gate arrays, transistors are arrayed in alternating rows of P-channel and N-channel transistors. A decoding scheme inverts the logic signal to each row of P-channel transistors to yield a functional ROM.

摘要翻译： 从门阵列导出静态只读存储器（ROM），其中P沟道晶体管（24）和N沟道晶体管（30）都用于将逻辑1或0传送到位线（Bitline0） 。 本发明使门阵列芯片中的栅极阵列晶体管的使用最大化，并且实现了每单位面积的高密度ROM位。 在CMOS门阵列中，晶体管排列成交替的P沟道和N沟道晶体管。 解码方案将逻辑信号反转到每行P沟道晶体管，以产生功能ROM。