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公开(公告)号：US5122476A
公开(公告)日：1992-06-16
申请号：US703185
申请日：1991-05-20
IPC分类号： H01L27/108
CPC分类号： H01L27/10829 , H01L27/10808
摘要： A double dynamic random access memory (DRAM) cell comprising two vertically stacked access transistors and storage capacitors. A first access transistor is formed on a silicon substrate. A seed contact to the first access transistor is then utilized for growing an intermediate silicon substrate by Confined Lateral Selective Epitaxial Overgrowth (CLSEG). A second access transistor is formed upon the intermediate silicon substrate. A storage capacitor for the first access transistor may be formed as a trench capacitor in the silicon substrate. A storage capacitor for the second access transistor may be stacked on the second access transistor. A common buried bit line connects the two access transistors.
摘要翻译： 一种双动态随机存取存储器（DRAM）单元，包括两个垂直堆叠的存取晶体管和存储电容器。 第一存取晶体管形成在硅衬底上。 然后，通过限制横向选择性外延生长（CLSEG），将第一存取晶体管的种子接触用于生长中间硅衬底。 第二存取晶体管形成在中间硅衬底上。 可以在硅衬底中形成用于第一存取晶体管的存储电容器作为沟槽电容器。 用于第二存取晶体管的存储电容器可以堆叠在第二存取晶体管上。 公共埋地位线连接两个存取晶体管。
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公开(公告)号：US5089986A
公开(公告)日：1992-02-18
申请号：US637108
申请日：1991-01-02
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817
摘要： A mushroom double stacked capacitor (mushroom cell) using a modified stacked capacitor storage cell fabrication process. The mushroom cell is made up of polysilicon structure, having a mushroom extended V-shaped cross-section. The storage node plate of the mushroom cell is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The shape of the polysilicon structure increases storage capability 200% or more without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.
摘要翻译： 一种采用改进的堆叠式电容器蓄电池制造工艺的蘑菇双层电容器（蘑菇电池）。 蘑菇细胞由多晶硅结构组成，具有蘑菇形延伸的V形横截面。 蘑菇细胞的存储节点板被夹在其间的电介质多晶硅覆盖，并通过埋入接触连接到进入装置的有效区域。 板延伸到相邻的存储节点，但是通过小于给定光刻技术的临界分辨率尺寸与相邻节点隔离。 多晶硅结构的形状提高了200％以上的存储能力，而不会扩大为正常埋地数字线叠层电容器单元所限定的表面积。
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公开(公告)号：US5234855A
公开(公告)日：1993-08-10
申请号：US633595
申请日：1990-12-21
申请人： Howard E. Rhodes , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Gurtej S. Sandhu
发明人： Howard E. Rhodes , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Gurtej S. Sandhu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , H01L28/91
摘要： A stacked comb spacer capacitor (SCSC) using a modified stacked capacitor storage cell fabrication process. The SCSC is made up of polysilicon structure, having a spiked v-shaped (or comb-shaped) cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The creation of the spiked polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell. Removing the dielectric residing under the backside of the storage node cell plate and filling that area with polysilicon increases storage capacity by an additional 50% or more.
摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠梳状间隔电容器（SCSC）。 SCSC由多晶硅结构组成，具有加深的V形（或梳状）横截面，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点和介于其间的电介质。 掺杂多晶硅结构的产生增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器单元定义的表面积。 去除位于存储节点单元板背面的电介质并用多晶硅填充该区域将存储容量提高了50％以上。
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公开(公告)号：US5108943A
公开(公告)日：1992-04-28
申请号：US763845
申请日：1991-09-23
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A mushroom double stacked capacitor (mushroom cell) using a modified stacked capacitor storage cell fabrication process. The mushroom cell is made up of polysilicon structure, having a mushroom extended V-shaped cross-section. The storage node plate of the mushroom cell is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The shape of the polysilicon structure increases storage capability 200% or more without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.
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公开(公告)号：US5057888A
公开(公告)日：1991-10-15
申请号：US646261
申请日：1991-01-28
IPC分类号： H01L27/108
CPC分类号： H01L27/10829 , H01L27/10808
摘要： A double dynamic random access memory (DRAM) cell comprising two vertically stacked access transistors and storage capacitors. A first access transistor is formed on a silicon substrate. A seed contact to the first access transistor is then utilized for growing an intermediate silicon substrate by Confined Lateral Selective Epitaxial Overgrowth (CLSEG). A second access transistor is formed upon the intermediate silicon substrate. A storage capacitor for the first access transistor may be formed as a trench capacitor in the silicon substrate. A storage capacitor for the second access transistor may be stacked on the second access transistor. A common buried bit line connects the two access transistors.
摘要翻译： 一种双动态随机存取存储器（DRAM）单元，包括两个垂直堆叠的存取晶体管和存储电容器。 第一存取晶体管形成在硅衬底上。 然后，通过限制横向选择性外延生长（CLSEG），将第一存取晶体管的种子接触用于生长中间硅衬底。 第二存取晶体管形成在中间硅衬底上。 可以在硅衬底中形成用于第一存取晶体管的存储电容器作为沟槽电容器。 用于第二存取晶体管的存储电容器可以堆叠在第二存取晶体管上。 公共埋地位线连接两个存取晶体管。
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公开(公告)号：US5084406A
公开(公告)日：1992-01-28
申请号：US724026
申请日：1991-07-01
IPC分类号： G11C11/401 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/10 , H01L27/108
CPC分类号： H01L23/53271 , H01L21/768 , H01L23/5283 , H01L2924/0002
摘要： A DRAM fabrication process is disclosed for constructing a reduced resistance digit-line. The digit-line is so constructed as to maintain low resistance as it crosses the gaps between word-lines. By bridging gaps having a dimension less than or falling below a calculated critical gap spacing, and following the contours of gaps having a dimension greater or falling above that critical gap dimension, the digit-line resistance can be minimized.
摘要翻译： 公开了用于构造减小电阻数字线的DRAM制造工艺。 数字线被构造成当它跨越字线之间的间隙时保持低电阻。 通过桥接具有小于或低于计算的临界间隙的尺寸的间隙，并且跟随具有大于或低于该临界间隙尺寸的尺寸的间隙的轮廓，可以使数字线电阻最小化。
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7.发明授权Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor 失效用于增加半导体处理中的导电材料的电容表面积的方法和堆叠的存储单元电容器
公开(公告)号：US5170233A
公开(公告)日：1992-12-08
申请号：US722854
申请日：1991-06-27
IPC分类号： H01L21/02 , H01L27/108 , H01L29/92
CPC分类号： H01L27/10817 , H01L28/87 , H01L28/90
摘要： A method of fabricating a semiconductor wafer comprises providing an electrically conductive area on a semiconductor wafer. Multiple alternating layers of first and second materials are provided atop the wafer. The first and second materials need be selectively etchable relative to one another. The multiple layers are etched and the electrically conductive area upwardly exposed to define exposed edges of the multiple layers projecting upwardly from the electrically conductive area. One of the first or second materials is selectively isotropically etched relative to the other to produce indentations which extend generally laterally into the exposed edges of the multiple layers. A layer of electrically conductive material is applied atop the wafer and electrically conductive area, and fills the exposed edge indentations. The electrically conductive material is etched to leave conductive material extending upwardly from the electrically conductive area adjacent the multiple layer edges and within the indentations. The multiple layers are etched from the wafer to leave upwardly projecting conductive material having lateral projections extending therefrom. Such material is used to form the lower plate of a capacitor.
摘要翻译： 制造半导体晶片的方法包括在半导体晶片上提供导电区域。 将第一和第二材料的多个交替层设置在晶片顶部。 第一和第二材料需要相对于彼此可选择性地蚀刻。 蚀刻多个层，并且导电区域向上暴露以限定从导电区域向上突出的多个层的暴露边缘。 第一或第二材料之一相对于另一材料选择性地各向同性地蚀刻，以产生大致横向延伸到多层的暴露边缘的凹痕。 将一层导电材料施加在晶片和导电区域顶部，并填充暴露的边缘凹陷。 蚀刻导电材料以留下从邻近多层边缘和凹陷内的导电区域向上延伸的导电材料。 从晶片上蚀刻多层以留下向上突出的具有从其延伸的侧向突起的导电材料。 这种材料用于形成电容器的下板。
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8.发明授权
公开(公告)号：US5321648A
公开(公告)日：1994-06-14
申请号：US48168
申请日：1993-04-15
IPC分类号： H01L27/108 , G11C11/24
CPC分类号： H01L27/10817
摘要： A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠的v电池（SVC）电容器。 SVC电容器由具有V形横截面的多晶硅结构组成，位于掩埋接触处并且延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。 多晶硅结构的添加增加了存储能力70％，而不会扩大为正常层叠电容器单元所定义的表面积。
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公开(公告)号：US5234858A
公开(公告)日：1993-08-10
申请号：US614770
申请日：1990-11-16
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817
摘要： A stacked surrounding wall capacitor (SSWC) using a modified stacked capacitor storage cell fabrication process. The SSWC is made up of polysilicon structure, having an elongated v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.
摘要翻译： 堆叠围墙电容器（SSWC）采用改进的叠层电容器存储单元制造工艺。 SSWC由多晶硅结构组成，具有细长的V形横截面，位于掩埋接触处并延伸到覆盖有多个介质的介电层之间的多晶硅的相邻存储节点。 多晶硅结构的添加增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器电池定义的表面积。
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公开(公告)号：US5100825A
公开(公告)日：1992-03-31
申请号：US614892
申请日：1990-11-16
IPC分类号： H01L21/02
摘要： A stacked surrounding reintrant wall capacitor (SSRWC) using a modified stacked capacitor storage cell fabrication process. The SSRWC is made up of polysilicon structure, having an elongated v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠围绕的重入壁电容器（SSRWC）。 SSRWC由多晶硅结构组成，具有细长的V形横截面，位于掩埋接触处并且延伸到由多晶硅覆盖的相邻存储节点，介电夹在其间。 多晶硅结构的添加增加了存储能力50％，而不会增加正常堆叠电容器单元所定义的表面积。
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