公开(公告)号：US06197662B1

公开(公告)日：2001-03-06

申请号：US09288881

申请日：1999-04-09

申请人： Hiang C. Chan

发明人： Hiang C. Chan

IPC分类号： H01L2176

CPC分类号： H01L21/28202 ,  H01L21/32 ,  H01L21/76202 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor processing method of forming field isolation oxide relative to a silicon substrate includes, i) rapid thermal nitridizing an exposed silicon substrate surface to form a base silicon nitride layer on the silicon substrate; ii) providing a silicon nitride masking layer over the nitride base layer, the base and masking silicon nitride layers comprising a composite of said layers of a combined thickness effective to restrict appreciable oxidation of silicon substrate thereunder when the substrate is exposed to LOCOS conditions; and iii) exposing the substrate to oxidizing conditions effective to form field isolation oxide on substrate areas not masked by the base and masking silicon nitride layers composite. Further, a semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate includes, a) masking a first portion of a semiconductor substrate with a composite comprising a first nitride layer, a polysilicon layer over the nitride layer, and a second nitride layer over the polysilicon layer; and leaving a second portion of the semiconductor substrate unmasked by said composite; and b) exposing the semiconductor substrate to oxidizing conditions effective to form field isolation oxide in the second substrate portion.

摘要翻译： 相对于硅衬底形成场隔离氧化物的半导体处理方法包括：i）快速热氮化暴露的硅衬底表面以在硅衬底上形成基底氮化硅层; ii）在氮化物基底层上提供氮化硅掩蔽层，所述基底和掩模氮化硅层包括具有组合厚度的所述层的复合材料，当所述衬底暴露于LOCOS条件时，其有效地限制硅衬底的明显氧化; 以及iii）将衬底暴露于有效地在未被基底掩蔽的掩模和掩蔽氮化硅层复合材料的衬底区域上形成场隔离氧化物的氧化条件。 此外，相对于半导体衬底形成场隔离氧化物的半导体处理方法包括：a）用包含第一氮化物层，氮化物层上的多晶硅层和第二氮化物层的复合材料掩蔽半导体衬底的第一部分 多晶硅层; 并留下未被所述复合材料掩蔽的半导体衬底的第二部分; 以及b）将所述半导体衬底暴露于在所述第二衬底部分中有效形成场隔离氧化物的氧化条件。

公开(公告)号：US5089986A

公开(公告)日：1992-02-18

申请号：US637108

申请日：1991-01-02

申请人： Gurtej S. Sandhu ,  Pierre C. Fazan ,  Yauh-Ching Liu ,  Hiang C. Chan

发明人： Gurtej S. Sandhu ,  Pierre C. Fazan ,  Yauh-Ching Liu ,  Hiang C. Chan

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： A mushroom double stacked capacitor (mushroom cell) using a modified stacked capacitor storage cell fabrication process. The mushroom cell is made up of polysilicon structure, having a mushroom extended V-shaped cross-section. The storage node plate of the mushroom cell is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The shape of the polysilicon structure increases storage capability 200% or more without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

摘要翻译： 一种采用改进的堆叠式电容器蓄电池制造工艺的蘑菇双层电容器（蘑菇电池）。 蘑菇细胞由多晶硅结构组成，具有蘑菇形延伸的V形横截面。 蘑菇细胞的存储节点板被夹在其间的电介质多晶硅覆盖，并通过埋入接触连接到进入装置的有效区域。 板延伸到相邻的存储节点，但是通过小于给定光刻技术的临界分辨率尺寸与相邻节点隔离。 多晶硅结构的形状提高了200％以上的存储能力，而不会扩大为正常埋地数字线叠层电容器单元所限定的表面积。

公开(公告)号：US5122476A

公开(公告)日：1992-06-16

申请号：US703185

申请日：1991-05-20

申请人： Pierre C. Fazan ,  Hiang C. Chan ,  Yauh-Ching Liu ,  Gurtej S. Sandhu ,  Howard E. Rhodes

发明人： Pierre C. Fazan ,  Hiang C. Chan ,  Yauh-Ching Liu ,  Gurtej S. Sandhu ,  Howard E. Rhodes

IPC分类号： H01L27/108

CPC分类号： H01L27/10829 ,  H01L27/10808

摘要： A double dynamic random access memory (DRAM) cell comprising two vertically stacked access transistors and storage capacitors. A first access transistor is formed on a silicon substrate. A seed contact to the first access transistor is then utilized for growing an intermediate silicon substrate by Confined Lateral Selective Epitaxial Overgrowth (CLSEG). A second access transistor is formed upon the intermediate silicon substrate. A storage capacitor for the first access transistor may be formed as a trench capacitor in the silicon substrate. A storage capacitor for the second access transistor may be stacked on the second access transistor. A common buried bit line connects the two access transistors.

摘要翻译： 一种双动态随机存取存储器（DRAM）单元，包括两个垂直堆叠的存取晶体管和存储电容器。 第一存取晶体管形成在硅衬底上。 然后，通过限制横向选择性外延生长（CLSEG），将第一存取晶体管的种子接触用于生长中间硅衬底。 第二存取晶体管形成在中间硅衬底上。 可以在硅衬底中形成用于第一存取晶体管的存储电容器作为沟槽电容器。 用于第二存取晶体管的存储电容器可以堆叠在第二存取晶体管上。 公共埋地位线连接两个存取晶体管。

公开(公告)号：US5082797A

公开(公告)日：1992-01-21

申请号：US645086

申请日：1991-01-22

申请人： Hiang C. Chan ,  Pierre Fazan ,  Yauh-Ching Liu

发明人： Hiang C. Chan ,  Pierre Fazan ,  Yauh-Ching Liu

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

摘要： A stacked textured container capacitor (STCC) using a modified stacked capacitor storage cell fabrication process. The STCC is made up of a texturized polysilicon structure, having an elongated u-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. With the 3-dimensional shape and texturized surface of a polysilicon storage node plate substantial capacitor plate surface area of 200% or more is gained at the storage node.

摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠纹理容器电容器（STCC）。 STCC由纹理化的多晶硅结构组成，具有细长的u形横截面，位于掩埋的接触处并且延伸到由多晶硅覆盖的相邻存储节点，介电夹在其间。 在多晶硅储存节点板的3维形状和纹理化表面上，在存储节点处获得基本上电容器板表面积为200％以上的表面积。

公开(公告)号：US5358894A

公开(公告)日：1994-10-25

申请号：US175481

申请日：1993-12-30

申请人： Pierre Fazan ,  Viju Mathews ,  Gurtej S. Sandhu ,  Mohammed Anjum ,  Hiang C. Chan

发明人： Pierre Fazan ,  Viju Mathews ,  Gurtej S. Sandhu ,  Mohammed Anjum ,  Hiang C. Chan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02238 ,  H01L21/02299 ,  H01L21/31662 ,  H01L21/76213 ,  Y10S148/116 ,  Y10S148/163

摘要： A LOCOS process is enhanced by enhancing the depth of field oxide in regions having a narrow field oxide width. Subsequent to forming a pattern of nitride to define the field oxide and active area, photoresist is applied to selected areas of the wafer. An impurity is then applied to the underlying semiconductor substrate in areas not protected by photoresist and nitride. The impurity results in an enhanced oxidation rate and therefore compensates for a thinning effect in selected field oxide areas, such as those having a narrow width. Subsequent formation of the field oxide results in the doped material being consumed by the oxide.

摘要翻译： 通过在具有窄场氧化物宽度的区域中增强场氧化物来增强LOCOS工艺。 在形成氮化物图案以限定场氧化物和有源区域之后，将光致抗蚀剂施加到晶片的选定区域。 然后在不受光致抗蚀剂和氮化物保护的区域中将杂质施加到下面的半导体衬底。 杂质导致增强的氧化速率，因此补偿了选择的场氧化物区域（例如具有窄宽度的区域）中的稀化效应。 随后形成场氧化物导致掺杂材料被氧化物消耗。

公开(公告)号：US5262343A

公开(公告)日：1993-11-16

申请号：US852822

申请日：1992-03-06

申请人： Howard E. Rhodes ,  Pierre Fazan ,  Hiang C. Chan ,  Charles H. Dennison ,  Yauh-Ching Liu

发明人： Howard E. Rhodes ,  Pierre Fazan ,  Hiang C. Chan ,  Charles H. Dennison ,  Yauh-Ching Liu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L28/40

摘要： This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked capacitor cells using a high dielectric constant material as a storage cell dielectric and a combination of conductively doped polysilicon and metal silicide as the capacitor plates of a storage cell for use in high-density dynamic random access memory (DRAM) arrays. The present invention teaches how to fabricate three-dimensional stacked capacitors by modifying an existing stacked capacitor fabrication process to construct the three-dimensional stacked capacitor cell incorporating a high dielectric constant material as the cell dielectric that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10.times. or more over that of a conventional 3-dimensional storage cell is gained by using a high dielectric constant material as the storage cell dielectric.

摘要翻译： 本发明涉及半导体电路存储器存储器件，更具体地说，涉及使用高介电常数材料作为存储单元电介质和导电掺杂多晶硅和金属硅化物的组合来开发三维叠层电容器单元的方法，作为电容器板 用于高密度动态随机存取存储器（DRAM）阵列的存储单元。 本发明教导了如何通过修改现有的层叠电容器制造工艺来制造三维层叠电容器，以构建结合有高介电常数材料的三维叠层电容器单元作为电池电介质，其将使得更密集的存储单元制造以最小的增加 整体内存阵列尺寸。 通过使用高介电常数材料作为存储单元电介质，获得比常规3维存储单元的电容增益高3至10倍或更多的电容增益。

公开(公告)号：US5236860A

公开(公告)日：1993-08-17

申请号：US799461

申请日：1991-11-26

申请人： Pierre Fazan ,  Gurtej S. Sandhu ,  Hiang C. Chan ,  Yauh-Ching Liu

发明人： Pierre Fazan ,  Gurtej S. Sandhu ,  Hiang C. Chan ,  Yauh-Ching Liu

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A lateral extension stacked capacitor (LESC) using a modified stacked capacitor storage cell fabrication process. The LESC is made up of polysilicon structure, having a spherical ended v-shaped cross-section. The storage node plate of the LESC is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

摘要翻译： 一种侧向延伸堆叠电容器（LESC），采用改进的堆叠电容器存储单元制造工艺。 LESC由多晶硅结构组成，具有球形末端的V形横截面。 LESC的存储节点板由介质夹在其间的多晶硅覆盖，并通过埋入触点连接到接入设备的有源区。 板延伸到相邻的存储节点，但是通过小于给定光刻技术的临界分辨率尺寸与相邻节点隔离。 多晶硅结构的添加增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器电池定义的表面积。

公开(公告)号：US5137842A

公开(公告)日：1992-08-11

申请号：US699291

申请日：1991-05-10

申请人： Hiang C. Chan ,  Pierre Fazan

发明人： Hiang C. Chan ,  Pierre Fazan

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked H-Cell (SHC). The SHC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SHC is made up of a polysilicon storage node structure having a H-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SHC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an H-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

摘要翻译： 修改现有的堆叠电容器制造工艺以构建称为堆叠H电池（SHC）的三维叠层电容器。 SHC设计定义了在本发明中用于DRAM处理的电容器存储单元。 SHC由具有H形横截面上部的多晶硅存储节点结构构成，下部向下延伸并通过埋入触点与有源区接触。 多晶硅存储节点结构由多晶硅覆盖，电介质夹在其间以形成完整的SHC电容器。 具有H形横截面的新颖的三维多晶硅储存节点板允许在存储节点处获得大于常规STC的电容器板表面积为200％或更大的电容器板表面积。

公开(公告)号：US5084406A

公开(公告)日：1992-01-28

申请号：US724026

申请日：1991-07-01

申请人： Howard E. Rhodes ,  Pierre C. Fazan ,  Hiang C. Chan ,  Charles H. Dennison ,  Yauh-Ching Liu

发明人： Howard E. Rhodes ,  Pierre C. Fazan ,  Hiang C. Chan ,  Charles H. Dennison ,  Yauh-Ching Liu

IPC分类号： G11C11/401 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L23/53271 ,  H01L21/768 ,  H01L23/5283 ,  H01L2924/0002

摘要： A DRAM fabrication process is disclosed for constructing a reduced resistance digit-line. The digit-line is so constructed as to maintain low resistance as it crosses the gaps between word-lines. By bridging gaps having a dimension less than or falling below a calculated critical gap spacing, and following the contours of gaps having a dimension greater or falling above that critical gap dimension, the digit-line resistance can be minimized.

摘要翻译： 公开了用于构造减小电阻数字线的DRAM制造工艺。 数字线被构造成当它跨越字线之间的间隙时保持低电阻。 通过桥接具有小于或低于计算的临界间隙的尺寸的间隙，并且跟随具有大于或低于该临界间隙尺寸的尺寸的间隙的轮廓，可以使数字线电阻最小化。

公开(公告)号：US6107176A

公开(公告)日：2000-08-22

申请号：US78335

申请日：1998-05-13

申请人： Pierre C. Fazan ,  Hiang C. Chan

发明人： Pierre C. Fazan ,  Hiang C. Chan

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061

摘要： A method of fabricating a gate having a barrier layer of titanium silicide is comprised of the steps of forming a layer of gate oxide. The gate oxide may be formed using a standard LOCOS process. A layer of doped polysilicon is deposited over the layer of gate oxide. A layer of titanium silicide is formed in a predetermined relationship with respect the layer of doped polysilicon, i.e., it may be deposited on top of the polysilicon or formed in a top surface of the polysilicon layer. A layer of tungsten silicide is deposited on top of the layer of titanium silicide. The layers of gate oxide, doped polysilicon, titanium silicide, and tungsten silicide are etched to form the gate. A gate thus fabricated is also disclosed.

摘要翻译： 制造具有硅化钛阻挡层的栅极的方法包括形成栅氧化层的步骤。 栅极氧化物可以使用标准LOCOS工艺形成。 掺杂多晶硅层沉积在栅极氧化物层上。 相对于掺杂多晶硅层以预定的关系形成硅化钛层，即其可沉积在多晶硅的顶部或形成在多晶硅层的顶表面中。 在硅化钛层的顶部上沉积一层硅化钨。 蚀刻栅极氧化物，掺杂多晶硅，硅化钛和硅化钨的层以形成栅极。 还公开了如此制造的栅极。