公开(公告)号：US20070255907A1

公开(公告)日：2007-11-01

申请号：US11413243

申请日：2006-04-28

申请人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul Loewenstein ,  Robert Cypher ,  Zoran Radovic

发明人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul Loewenstein ,  Robert Cypher ,  Zoran Radovic

IPC分类号： G06F13/28

CPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F12/0822 ,  G06F12/0897

摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值相匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

公开(公告)号：US07412567B2

公开(公告)日：2008-08-12

申请号：US11413243

申请日：2006-04-28

申请人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

发明人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F12/0822 ,  G06F12/0897

摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

公开(公告)号：US20080010417A1

公开(公告)日：2008-01-10

申请号：US11859955

申请日：2007-09-24

申请人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Kevin Moore

发明人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Kevin Moore

IPC分类号： G06F12/00

CPC分类号： G06F12/0808 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0822 ,  G06F12/1425 ,  G06F2212/1008

摘要： In one embodiment, a method comprises communicating with one or more other nodes in a system from a first node in the system in response to a trap experienced by a processor in the first node during a memory operation, wherein the trap is signalled in the processor in response to one or more permission bits stored with a cache line in a cache accessible during performance of the memory operation; determining that the cache line is part of a memory transaction in a second node that is one of the other nodes, wherein a memory transaction comprises two or more memory operations that appear to execute atomically in isolation; and resolving a conflict between the memory operation and the memory transaction.

摘要翻译： 在一个实施例中，一种方法包括响应于在存储器操作期间由第一节点中的处理器经历的陷阱而从系统中的第一节点与系统中的一个或多个其他节点进行通信，其中在处理器中用信号通知陷阱 响应于在执行存储器操作期间可访问的高速缓存中存储有高速缓存行的一个或多个许可位; 确定所述高速缓存行是作为其他节点之一的第二节点中的存储器事务的一部分，其中存储器事务包括看起来孤立地原子地执行的两个或多个存储器操作; 并解决内存操作和内存事务之间的冲突。

公开(公告)号：US20070260821A1

公开(公告)日：2007-11-08

申请号：US11417640

申请日：2006-05-04

申请人： Hakan Zeffer ,  Anders Landin ,  Erik Hagersten

发明人： Hakan Zeffer ,  Anders Landin ,  Erik Hagersten

IPC分类号： G06F12/00

CPC分类号： G06F12/0815

摘要： In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a remote address or a local address. A first portion of the memory in the node is allocated to store copies of remote data and a remaining portion stores local data. The control unit is configured to write writeback data to a location in the first portion. The writeback data corresponds to a writeback request from the intranode interconnect that has an associated remote address detected by the logic. The control unit is configured to determine the location responsive to the associated remote address and one or more indicators that identify the first portion in the memory.

摘要翻译： 在一个实施例中，用于多节点计算机系统中的节点的存储器控​​制器包括逻辑和控制单元。 逻辑被配置为确定与内部控制器在内部网络互连上接收到的请求对应的地址是远程地址还是本地地址。 分配节点中的存储器的第一部分以存储远程数据的副本，并且剩余部分存储本地数据。 控制单元被配置为将写回数据写入第一部分中的位置。 回写数据对应于具有由逻辑检测到的相关联的远程地址的内部网络互连的回写请求。 控制单元被配置为确定响应于相关联的远程地址的位置和识别存储器中的第一部分的一个或多个指示符。

公开(公告)号：US20050044174A1

公开(公告)日：2005-02-24

申请号：US10821729

申请日：2004-04-09

申请人： Anders Landin ,  Robert Cypher ,  Erik Hagersten ,  Ashok Singhal

发明人： Anders Landin ,  Robert Cypher ,  Erik Hagersten ,  Ashok Singhal

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0817 ,  G06F12/0813 ,  G06F12/0831

摘要： A system may include a plurality of nodes coupled by an inter-node network. Each of the nodes includes several active devices, an interface to the inter-node network, and an address network coupling the active devices to the interface. An active device included in one of the nodes initiates a transaction by sending either a first type of address packet or a second type of address packet on the address network dependent on whether the active device is included in a multi-node system. The first type of address packet is sent if the active device is included in a multi-node system and is not snooped by other active devices in the same node as the active device. The second type of address packet, sent if the active device is included in a single node system, is snooped by other active devices in the same node as the active device.

摘要翻译： 系统可以包括由节点间网络耦合的多个节点。 每个节点包括若干活动设备，节点间网络的接口以及将活动设备耦合到接口的地址网络。 包括在其中一个节点中的活动设备通过在地址网络上发送第一类型的地址分组或第二类型的地址分组来发起交易，这取决于活动设备是否包括在多节点系统中。 如果活动设备包括在多节点系统中并且不与主动设备在同一节点中的其他活动设备进行窥探，则发送第一类地址分组。 如果活动设备包含在单个节点系统中，则发送的第二种类型的地址分组被与活动设备在同一节点中的其他活动设备进行探测。

公开(公告)号：US20050005075A1

公开(公告)日：2005-01-06

申请号：US10821370

申请日：2004-04-09

申请人： Anders Landin ,  Robert Cypher ,  David Wood ,  Erik Hagersten ,  Mark Hill

发明人： Anders Landin ,  Robert Cypher ,  David Wood ,  Erik Hagersten ,  Mark Hill

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0817

摘要： A system may include a node and an additional node coupled by an inter-node network. The node may include an active device, an interface to the inter-node network, a memory, and an address network coupling the active device, the interface, and the memory. The active device may send an address packet to initiate a transaction to gain an access right to a coherency unit. In response to receiving the address packet, the memory is configured to send data corresponding to the coherency unit to the active device dependent on memory response information associated with the coherency unit. If the transaction cannot be satisfied within the node, the memory is configured to forward a report corresponding to the address packet to the interface. In response to the report, the interface is configured to send the additional node a coherency message requesting the access right via the inter-node network.

摘要翻译： 系统可以包括由节点间网络耦合的节点和附加节点。 节点可以包括活动设备，到节点间网络的接口，存储器和耦合有源设备，接口和存储器的地址网络。 活动设备可以发送地址分组以发起事务以获得对一致性单元的访问权限。 响应于接收到地址分组，存储器被配置为根据与一致性单元相关联的存储器响应信息将对应于一致性单元的数据发送到活动设备。 如果在节点内不能满足事务，则内存被配置为将与地址分组相对应的报告转发到接口。 响应于该报告，该接口被配置为经由节点间网络向附加节点发送请求访问权限的一致性消息。

公开(公告)号：US07676636B2

公开(公告)日：2010-03-09

申请号：US11775693

申请日：2007-07-10

申请人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin

发明人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin

IPC分类号： G06F12/08

CPC分类号： G06F12/08 ,  G06F12/0842 ,  G06F12/1045 ,  G06F12/1081

摘要： Embodiments of the present invention implement virtual transactional memory using cache line marking. The system starts by executing a starvation-avoiding transaction for a thread. While executing the starvation-avoiding transaction, the system places starvation-avoiding load-marks on cache lines which are loaded from and places starvation-avoiding store-marks on cache lines which are stored to. Next, while swapping a page out of a memory and to a disk during the starvation-avoiding transaction, the system determines if one or more cache lines in the page have a starvation-avoiding load-mark or a starvation-avoiding store-mark. If so, upon swapping the page into the memory from the disk, the system places a starvation-avoiding load-mark on each cache line that had a starvation-avoiding load-mark and places a starvation-avoiding store-mark on each cache line that had a starvation-avoiding store-mark.

摘要翻译： 本发明的实施例使用高速缓存行标记来实现虚拟事务存储器。 系统通过执行线程的避免饥饿事务来启动。 在执行避免饥饿事务的同时，系统会在加载的缓存行上放置饥饿 - 避免加载标记，并将存储在缓存行上的饥饿 - 避免存储标记放置在缓存行上。 接下来，当在饥饿 - 避免交易期间将页面从存储器切换到磁盘时，系统确定页面中的一个或多个高速缓存行是否具有避免饥饿负载标记或避免饥饿的存储标记。 如果是这样，当将页面从磁盘交换到内存中时，系统会在每个具有饥饿 - 避免加载标记的缓存行上放置一个避免饥饿的加载标记，并在每条缓存行上放置一个避免饥饿的商标 有一个饥饿的避免商标。

公开(公告)号：US20090019231A1

公开(公告)日：2009-01-15

申请号：US11775693

申请日：2007-07-10

申请人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin

发明人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin

IPC分类号： G06F12/08

CPC分类号： G06F12/08 ,  G06F12/0842 ,  G06F12/1045 ,  G06F12/1081

摘要： Embodiments of the present invention implement virtual transactional memory using cache line marking. The system starts by executing a starvation-avoiding transaction for a thread. While executing the starvation-avoiding transaction, the system places starvation-avoiding load-marks on cache lines which are loaded from and places starvation-avoiding store-marks on cache lines which are stored to. Next, while swapping a page out of a memory and to a disk during the starvation-avoiding transaction, the system determines if one or more cache lines in the page have a starvation-avoiding load-mark or a starvation-avoiding store-mark. If so, upon swapping the page into the memory from the disk, the system places a starvation-avoiding load-mark on each cache line that had a starvation-avoiding load-mark and places a starvation-avoiding store-mark on each cache line that had a starvation-avoiding store-mark.

摘要翻译： 本发明的实施例使用高速缓存行标记来实现虚拟事务存储器。 系统通过执行线程的避免饥饿事务来启动。 在执行避免饥饿事务的同时，系统会在加载的缓存行上放置饥饿 - 避免加载标记，并将存储在缓存行上的饥饿 - 避免存储标记放置在缓存行上。 接下来，当在饥饿 - 避免交易期间将页面从存储器切换到磁盘时，系统确定页面中的一个或多个高速缓存行是否具有避免饥饿负载标记或避免饥饿的存储标记。 如果是这样，当将页面从磁盘交换到内存中时，系统会在每个具有饥饿 - 避免加载标记的缓存行上放置一个避免饥饿的加载标记，并在每条缓存行上放置一个避免饥饿的商标 有一个饥饿的避免商标。

公开(公告)号：US20100325374A1

公开(公告)日：2010-12-23

申请号：US12486138

申请日：2009-06-17

申请人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin ,  Haakan E. Zeffer

发明人： Robert E. Cypher ,  Shailender Chaudhry ,  Anders Landin ,  Haakan E. Zeffer

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0607 ,  G06F12/0646 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/10

摘要： Embodiments of the present invention provide a system that dynamically reconfigures memory. During operation, the system determines that a virtual memory page is to be reconfigured from an original virtual-address-to-physical-address mapping to a new virtual-address-to-physical-address mapping. The system then determines a new real address mapping for a set of virtual addresses in the virtual memory page by selecting a range of real addresses for the virtual addresses that are arranged according to the new virtual-address-to-physical-address mapping. Next, the system temporarily disables accesses to the virtual memory page. Then, the system copies data from real address locations indicated by the original virtual-address-to-physical-address mapping to real address locations indicated by the new virtual-address-to-physical-address mapping. Next, the system updates the real-address-to-physical-address mapping for the page, and re-enables accesses to the virtual memory page.

摘要翻译： 本发明的实施例提供一种动态重新配置存储器的系统。 在操作期间，系统确定虚拟内存页面将被重新配置为从原始虚拟地址到物理地址映射到新的虚拟地址到物理地址映射。 然后，系统通过选择根据新的虚拟地址到物理地址映射排列的虚拟地址的实际地址的范围来确定虚拟存储器页面中的一组虚拟地址的新的真实地址映射。 接下来，系统暂时禁用对虚拟内存页的访问。 然后，系统将由原始虚拟地址到物理地址映射指示的实际地址位置的数据复制到由新的虚拟地址到物理地址映射指示的实际地址位置。 接下来，系统更新页面的实际地址到物理地址映射，并重新启用对虚拟内存页的访问。

公开(公告)号：US20050005074A1

公开(公告)日：2005-01-06

申请号：US10817632

申请日：2004-04-02

申请人： Anders Landin ,  Erik Hagersten

发明人： Anders Landin ,  Erik Hagersten

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0817 ,  G06F12/0815 ,  G06F12/1072

摘要： A system may include a plurality of nodes. Each node may include an active device and a memory subsystem coupled to the active device. An active device in one of the nodes is configured to generate a global address that identifies a coherency unit and associated translation information identifying a translation function to be performed on the global address. A memory subsystem included in the node is configured to perform the translation function identified by the translation information on the global address to generate a physical address of the coherency unit within the memory subsystem. An additional memory subsystem included in an additional one of the nodes is configured to store the translation information identifying the translation function used in the node. In response to a request for access to the coherency unit, the additional memory subsystem is configured to send the translation information to the node.

摘要翻译： 系统可以包括多个节点。 每个节点可以包括活动设备和耦合到活动设备的存储器子系统。 其中一个节点中的活动设备被配置为生成识别一致性单元的全局地址和标识要在全局地址上执行的翻译功能的相关联的翻译信息。 包括在节点中的存储器子系统被配置为执行由全局地址上的翻译信息识别的翻译功能，以生成存储器子系统内的一致性单元的物理地址。 包括在另外一个节点中的附加存储器子系统被配置为存储标识在节点中使用的翻译函数的翻译信息。 响应于访问一致性单元的请求，附加存储器子系统被配置为将翻译信息发送到节点。