-
公开(公告)号：US08664742B2
公开(公告)日：2014-03-04
申请号：US12622939
申请日：2009-11-20
IPC分类号： H01L21/70
CPC分类号： H01L21/3065 , H01L21/76232 , H01L21/76283
摘要： An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls.
摘要翻译： 公开了一种中间半导体结构，其包括衬底和形成在衬底中的至少一个底切结构。 底切特征可以包括其中具有侧向空腔的垂直开口，垂直开口延伸到横向空腔下方。 横向空腔可以包括刻面侧壁。
-
公开(公告)号：US20100291742A1
公开(公告)日：2010-11-18
申请号：US12844722
申请日：2010-07-27
IPC分类号： H01L21/8242 , H01L21/30 , H01L21/44
CPC分类号： H01L27/10885 , H01L21/76254 , H01L21/84 , H01L27/10876 , H01L27/10882
摘要： A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
摘要翻译： 制造存储单元的方法包括在载体衬底上形成多个掺杂半导体层。 该方法还包括形成由绝缘材料隔开的多个数字线。 数字线排列在掺杂半导体层之上。 该方法还包括将多个沟槽蚀刻到掺杂半导体层中。 该方法还包括将绝缘材料沉积到多个沟槽中以形成多个电隔离的晶体管柱。 该方法还包括将形成在载体衬底上的结构的至少一部分结合到主体衬底。 该方法还包括从载体衬底分离载体衬底。
-
公开(公告)号：US07776715B2
公开(公告)日：2010-08-17
申请号：US11189945
申请日：2005-07-26
IPC分类号： H01L21/46
CPC分类号： H01L27/10885 , H01L21/76254 , H01L21/84 , H01L27/10876 , H01L27/10882
摘要： A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
摘要翻译： 制造存储单元的方法包括在载体衬底上形成多个掺杂半导体层。 该方法还包括形成由绝缘材料隔开的多个数字线。 数字线排列在掺杂半导体层之上。 该方法还包括将多个沟槽蚀刻到掺杂半导体层中。 该方法还包括将绝缘材料沉积到多个沟槽中以形成多个电隔离的晶体管柱。 该方法还包括将形成在载体衬底上的结构的至少一部分结合到主体衬底。 该方法还包括从载体衬底分离载体衬底。
-
公开(公告)号：US20120231602A1
公开(公告)日：2012-09-13
申请号：US13475716
申请日：2012-05-18
CPC分类号： H01L27/10885 , H01L21/76254 , H01L21/84 , H01L27/10876 , H01L27/10882
摘要： A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
摘要翻译： 制造存储单元的方法包括在载体衬底上形成多个掺杂半导体层。 该方法还包括形成由绝缘材料隔开的多个数字线。 数字线排列在掺杂半导体层之上。 该方法还包括将多个沟槽蚀刻到掺杂半导体层中。 该方法还包括将绝缘材料沉积到多个沟槽中以形成多个电隔离的晶体管柱。 该方法还包括将形成在载体衬底上的结构的至少一部分结合到主体衬底。 该方法还包括从载体衬底分离载体衬底。
-
公开(公告)号：US08187934B2
公开(公告)日：2012-05-29
申请号：US12844722
申请日：2010-07-27
IPC分类号： H01L21/8242
CPC分类号： H01L27/10885 , H01L21/76254 , H01L21/84 , H01L27/10876 , H01L27/10882
摘要： A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
摘要翻译： 制造存储单元的方法包括在载体衬底上形成多个掺杂半导体层。 该方法还包括形成由绝缘材料隔开的多个数字线。 数字线排列在掺杂半导体层之上。 该方法还包括将多个沟槽蚀刻到掺杂半导体层中。 该方法还包括将绝缘材料沉积到多个沟槽中以形成多个电隔离的晶体管柱。 该方法还包括将形成在载体衬底上的结构的至少一部分结合到主体衬底。 该方法还包括从载体衬底分离载体衬底。
-
公开(公告)号：US07786522B2
公开(公告)日：2010-08-31
申请号：US12405574
申请日：2009-03-17
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10823
摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.
摘要翻译： 存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。 数字线与相邻的存储器单元耦合，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。 形成存储单元的方法包括在衬底中形成掩埋的数字线，并且在与衬底数字线紧邻的衬底中形成垂直柱。 双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。
-
7.发明授权Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon 失效通过选择性蚀刻注入硅的凹坑来制造中间半导体结构的方法公开(公告)号：US07625776B2
公开(公告)日：2009-12-01
申请号：US11445911
申请日：2006-06-02
IPC分类号： H01L21/00
CPC分类号： H01L21/3065 , H01L21/76232 , H01L21/76283
摘要： A method of forming at least one undercut structure in a semiconductor substrate. The method comprises providing a semiconductor substrate, forming at least one doped region in the semiconductor substrate, and removing the at least one doped region to form at least one undercut structure in the semiconductor substrate. The at least one undercut structure may include at least one substantially vertical shelf, at least one substantially horizontal shelf, and at least one faceted surface. The at least one doped region may be formed by implanting an impurity in the semiconductor substrate, which is, optionally, annealed. The at least one doped region may be removed selective to the undoped portion of the semiconductor substrate by at least one of wet etching or dry etching. An intermediate semiconductor structure that comprises a single crystalline silicon substrate and at least one undercut structure formed in the single crystalline silicon substrate is also disclosed.
摘要翻译： 一种在半导体衬底中形成至少一个底切结构的方法。 所述方法包括提供半导体衬底，在所述半导体衬底中形成至少一个掺杂区域，以及移除所述至少一个掺杂区域以在所述半导体衬底中形成至少一个底切结构。 至少一个底切结构可以包括至少一个基本上垂直的搁架，至少一个基本上水平的搁架和至少一个小面。 可以通过在半导体衬底中注入杂质来形成至少一个掺杂区域，该衬底可选择地退火。 至少一个掺杂区域可以通过湿式蚀刻或干蚀刻中的至少一种来选择性地移除到半导体衬底的未掺杂部分。 还公开了包括单晶硅衬底和形成在单晶硅衬底中的至少一个底切结构的中间半导体结构。
-
公开(公告)号：US07504298B2
公开(公告)日：2009-03-17
申请号：US11711569
申请日：2007-02-26
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10823
摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.
摘要翻译： 存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。 数字线与相邻的存储器单元耦合，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。 形成存储单元的方法包括在衬底中形成掩埋的数字线，并且在与衬底数字线紧邻的衬底中形成垂直柱。 双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。
-
公开(公告)号：US20100290268A1
公开(公告)日：2010-11-18
申请号：US12844045
申请日：2010-07-27
IPC分类号： G11C11/24
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10823
摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.
摘要翻译： 存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。 数字线与相邻的存储器单元耦合，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。 形成存储单元的方法包括在衬底中形成掩埋的数字线，并且在与衬底数字线紧邻的衬底中形成垂直柱。 双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。
-
公开(公告)号：US20100065941A1
公开(公告)日：2010-03-18
申请号：US12622939
申请日：2009-11-20
IPC分类号： H01L29/06
CPC分类号： H01L21/3065 , H01L21/76232 , H01L21/76283
摘要： An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls.
摘要翻译： 公开了一种中间半导体结构，其包括衬底和形成在衬底中的至少一个底切结构。 底切特征可以包括其中具有侧向空腔的垂直开口，垂直开口延伸到横向空腔下方。 横向空腔可以包括刻面侧壁。
-
-
-
-
-
-
-
-
-
搜索结果
155 条记录 (耗时 0.023 秒)
