公开(公告)号：US09754666B2

公开(公告)日：2017-09-05

申请号：US15111194

申请日：2014-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent E. Buchanan ,  Martin Foltin ,  Jeffrey A. Lucas ,  Clinton H. Parker

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2213/77

Abstract: An apparatus includes a first resistive storage element and a second resistive storage element. The first and second resistive storage elements are coupled to column lines to of a crosspoint array to form a memory cell; and a ratio of resistances of the first and second resistive storage elements indicates a stored value for the memory cell.

公开(公告)号：US09911495B2

公开(公告)日：2018-03-06

申请号：US15114449

申请日：2014-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent E. Buchanan

IPC: G11C11/40 ,  G11C14/00 ,  G11C11/16 ,  G11C11/24 ,  G11C13/00

CPC classification number: G11C14/0045 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/24 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0052 ,  G11C2013/0092 ,  G11C2213/76

Abstract: A technique including using an array of memory cells for data storage. A given cell of the memory cells includes a capacitive storage element and a resistive storage element that is coupled in series with the capacitive storage element. The technique includes accessing the given memory cell to write a value to the given memory cell or read a value stored in the memory cell. The accessing includes applying a time varying voltage to the memory cell.