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公开(公告)号：US10275706B2
公开(公告)日：2019-04-30
申请号：US14845714
申请日：2015-09-04
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Matthew D. Pickett
Abstract: A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.
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公开(公告)号：US20140214738A1
公开(公告)日：2014-07-31
申请号：US13753152
申请日：2013-01-29
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Matthew D. Pickett
IPC: G06N3/04
CPC classification number: G06N3/0635 , G06N3/04 , G11C11/54 , G11C13/0002
Abstract: A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.
Abstract translation: 基于神经元的储层计算装置包括形成在互补金属氧化物半导体（CMOS）层中的支撑电路，连接到支持电路的输入节点和连接到支持电路的输出节点。 薄膜神经元节点设置在CMOS层上，神经元节点的第一部分连接到输入节点，并且神经元节点的第二部分连接到输出节点。 神经元节点之间的互连形成容纳来自输入节点的输入信号并在输出节点上输出信号的储层。 还提供了一种用于形成基于神经元的储层计算装置的方法。
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Patent Agency Ranking
公开(公告)号：US20150379395A1
公开(公告)日：2015-12-31
申请号：US14845714
申请日：2015-09-04
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Matthew D. Pickett
CPC classification number: G06N3/0635 , G06N3/04 , G11C11/54 , G11C13/0002
Abstract: A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.
Abstract translation: 基于神经元的储层计算装置包括形成在互补金属氧化物半导体（CMOS）层中的支撑电路，连接到支持电路的输入节点和连接到支持电路的输出节点。 薄膜神经元节点设置在CMOS层上，神经元节点的第一部分连接到输入节点，并且神经元节点的第二部分连接到输出节点。 神经元节点之间的互连形成容纳来自输入节点的输入信号并在输出节点上输出信号的储层。 还提供了一种用于形成基于神经元的储层计算装置的方法。
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公开(公告)号：US09165246B2
公开(公告)日：2015-10-20
申请号：US13753152
申请日：2013-01-29
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Matthew D. Pickett
CPC classification number: G06N3/0635 , G06N3/04 , G11C11/54 , G11C13/0002
Abstract: A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.
Abstract translation: 基于神经元的储层计算装置包括形成在互补金属氧化物半导体（CMOS）层中的支撑电路，连接到支持电路的输入节点和连接到支持电路的输出节点。 薄膜神经元节点设置在CMOS层上，神经元节点的第一部分连接到输入节点，并且神经元节点的第二部分连接到输出节点。 神经元节点之间的互连形成容纳来自输入节点的输入信号并在输出节点上输出信号的储层。 还提供了一种用于形成基于神经元的储层计算装置的方法。
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公开(公告)号：US20140215143A1
公开(公告)日：2014-07-31
申请号：US13755667
申请日：2013-01-31
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Matthew D. Pickett , Frederick Perner
IPC: G11C15/00
CPC classification number: G11C15/00 , G11C13/0007 , G11C15/046 , G11C2213/77
Abstract: Examples disclose a crossbar memory with a first crossbar to write data values corresponding to a word. The crossbar memory further comprises a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar. Additionally, the examples of the crossbar memory provide an output line that interconnects with the crossbars at junctions, to read the data values at the junctions. Further, the examples of the crossbar memory provide a logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar.
Abstract translation: 示例公开了具有第一交叉开关以写入对应于单词的数据值的交叉开关存储器。 交叉开关存储器还包括基本上平行于第一交叉开关的第二交叉开关，用于接收跨越第二横杆激活数据值的电压。 另外，交叉开关存储器的示例提供了一个输出线，其与交叉点处的交叉点相互连接，以便读取交汇处的数据值。 此外，交叉开关存储器的示例提供逻辑模块以确定第二交叉开关数据值是否对应于在第一横杠中写入的字。
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6.发明申请MEMRISTIVE DEVICES WITH LAYERED JUNCTIONS AND METHODS FOR FABRICATING THE SAME 审中-公开具有层状结构的测量装置及其制造方法公开(公告)号：US20150380464A1
公开(公告)日：2015-12-31
申请号：US14845636
申请日：2015-09-04
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Matthew D. Pickett , Jianhua Yang , Gilberto Medeiros Ribeiro
CPC classification number: H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1616
Abstract: Memristor systems and method for fabricating memristor system are disclosed. In one aspect, a memristor includes a first electrode, a second electrode, and a junction disposed between the first electrode and the second electrode. The junction includes at least one layer such that each layer has a plurality of dopant sub-layers disposed between insulating sub-layers. The sub-layers are oriented substantially parallel to the first and second electrodes.
Abstract translation: 记忆体系统和制造忆阻器系统的方法被公开。 一方面，忆阻器包括第一电极，第二电极和设置在第一电极和第二电极之间的结。 该结包括至少一个层，使得每个层具有设置在绝缘子层之间的多个掺杂剂子层。 子层的取向基本上平行于第一和第二电极。
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公开(公告)号：US20150194203A1
公开(公告)日：2015-07-09
申请号：US14416292
申请日：2012-07-27
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Matthew D. Pickett
CPC classification number: G11C11/39 , G11C11/40 , G11C13/0002 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2213/79 , G11C2213/82 , H01L27/1052 , H01L27/2436 , H01L27/26 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L47/00
Abstract: A memory cell includes a transistor with a first source/drain terminal spaced apart from a second source/drain terminal with a semiconductor material; a gate terminal located proximate the semiconductor material such that an increase in a gate terminal voltage increases a conductivity of the semiconductor material; and the first source/drain terminal being connected in series to a negative differential resistance material.
Abstract translation: 存储单元包括晶体管，其具有与具有半导体材料的第二源极/漏极端子间隔开的第一源极/漏极端子; 位于半导体材料附近的栅极端子，使得栅极端子电压的增加增加了半导体材料的导电性; 并且第一源极/漏极端子串联连接到负的差分电阻材料。
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