公开(公告)号：US20190293625A1

公开(公告)日：2019-09-26

申请号：US16464835

申请日：2017-10-12

Applicant: HITACHI, LTD.

Inventor： Mayu AOKI ,  Itaru YANAGI ,  Kunio HARADA ,  Kenichi TAKEDA

IPC: G01N33/487 ,  G01N27/447

Abstract: A method includes a step of introducing a solution between a substrate with a membrane in which the membrane is provided so as to close an opening and a substrate provided with an independent electrode in which the independent electrode is provided, a step of pressure bonding the substrate with the membrane and the substrate with the independent electrode through a partition wall, and a step of forming a sealed liquid tank surrounded by at least the membrane and the partition wall by the pressure bonding, and arraying of a solid-state type nanopore sequencer is simply performed.

公开(公告)号：US20160300764A1

公开(公告)日：2016-10-13

申请号：US14903026

申请日：2013-07-05

Applicant: HITACHI, LTD.

Inventor： Kenichi TAKEDA ,  Mayu AOKI ,  Kazuyuki HOZAWA

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311 ,  H01L23/522 ,  H01L21/3065 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/76816 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2924/15173 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A piece of first connecting wiring 210 is formed of a lower layer wiring close to a semiconductor element. A piece of second connecting wiring 220 is formed of an upper layer wiring far from the semiconductor element. A first opening that passes through a silicon substrate 100 and reaches the piece of first connecting wiring 210 and a second opening that passes through the silicon substrate 100 and reaches the piece of second connecting wiring 220 are formed from a back surface of the silicon substrate 100. After that, a first through silicon via 230 and a second through silicon via 240 are formed inside the first opening and the second opening, respectively. Accordingly, the first through silicon via 230 for propagating a signal, to be coupled to the piece of first connecting wiring 210, and the second through silicon via 240 for supplying a clock and a power source, to be coupled to the piece of second connecting wiring 220, can be formed. Therefore, a semiconductor device that satisfies a low parasitic resistance and a large allowable current can be achieved.

Abstract translation: 第一连接布线210由靠近半导体元件的下层布线形成。 第二连接布线220由远离半导体元件的上层布线形成。 通过硅基板100并到达第一连接布线210的第一开口和穿过硅基板100并到达第二连接布线220的第二开口由硅基板100的背面形成 之后，分别在第一开口和第二开口内形成第一贯通硅通孔230和第二硅通孔240。 因此，用于传播要耦合到第一连接布线210的信号的第一通孔硅通孔230和用于提供时钟和电源的第二通孔硅通孔240耦合到第二连接件 接线220可以形成。 因此，可以实现满足低寄生电阻和大容许电流的半导体器件。

公开(公告)号：US20190022647A1

公开(公告)日：2019-01-24

申请号：US16070602

申请日：2016-02-22

Applicant: HITACHI, LTD.

Inventor： Mayu AOKI ,  Kenichi TAKEDA ,  Kunio HARADA

IPC: B01L3/00 ,  G01N27/414 ,  G01N33/543

Abstract: A biological sample analysis chip including a first substrate, a membrane disposed on the first substrate, a first liquid tank which is provided with a first electrode, a plurality of second liquid tanks each of which is provided with at least one flow path and a second electrode; and a second substrate disposed below the first substrate, in which the plurality of second liquid tanks are substantially insulated from each other, the membrane disposed on the first substrate is disposed between the first liquid tank and the plurality of second liquid tanks so as to form a portion of the first liquid tank and a portion of the plurality of second liquid tanks, and the second substrate is provided with the at least one flow path and the second electrode so as to form a portion of the plurality of second liquid tanks.