公开(公告)号：US10056340B1

公开(公告)日：2018-08-21

申请号：US15346155

申请日：2016-11-08

Applicant: HRL Laboratories, LLC

Inventor： Hasan Sharifi ,  Keisuke Shinohara ,  Mary C. Montes ,  Charles McGuire ,  Wonill Ha ,  Jason May ,  Hooman Kazemi ,  Jongchan Kang ,  Robert G. Nagele

IPC: H01L23/00 ,  H01L23/66 ,  H01L21/683 ,  H01L21/311 ,  H01L23/12

CPC classification number: H01L23/66 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/12 ,  H01L23/367 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/80 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2223/6672

Abstract: An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dialectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

公开(公告)号：US09530708B1

公开(公告)日：2016-12-27

申请号：US13906750

申请日：2013-05-31

Applicant: HRL Laboratories, LLC

Inventor： Hasan Sharifi ,  Keisuke Shinohara ,  Mary C. Montes ,  Charles McGuire ,  Wonill Ha ,  Jason May ,  Hooman Kazemi ,  Jongchan Kang ,  Robert G. Nagele

IPC: H01L21/00 ,  H01L23/12 ,  H01L21/58

CPC classification number: H01L23/66 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/12 ,  H01L23/367 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/80 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2223/6672

Abstract: An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dielectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

Abstract translation: 一种电子电路，包括：集成电路芯片，所述集成电路芯片具有顶面; 芯片顶面的部分由与集成电路电连接的第一金属层覆盖; 以及在所述第一金属层的旁边和顶部形成在所述芯片的上表面上的介电层; 其中所述电介质层平行于所述芯片的所述顶面延伸超过所述芯片的边缘，所述第一金属层在所述电介质层中延伸超过所述芯片的边缘; 并且其中介电层的顶表面的部分被第二金属层覆盖，第一和第二金属层的部分通过电介质层电连接。