公开(公告)号：US09171247B1

公开(公告)日：2015-10-27

申请号：US13747987

申请日：2013-01-23

Applicant: HRL Laboratories, LLC

Inventor： Heiko Hoffmann ,  Hooman Kazemi

IPC: G06N3/02 ,  G06K9/62 ,  G06K9/00

CPC classification number: G06N3/02 ,  G06F17/30277 ,  G06K9/00201 ,  G06K9/62 ,  G06K9/6202

Abstract: Described is a pattern matching system for matching a test image with a 3D template. The system is initiated by generating a library of templates (each individual template is a three-dimensional array, with each pixel in the array representing a value at a particular x, y, and z coordinate). Each column of pixels along one axis (e.g., z) is converted into a neural input. Each neural input is fed through a neural network to establish a delayed connection between each neural input and output neuron and to generate a template neural network. Separately, a test image is converted into neural inputs. The neural inputs of the test image are input the template neural network to generate output neurons. The output neurons are evaluated to identify a location of the template in the test image.

Abstract translation: 描述了用于将测试图像与3D模板相匹配的模式匹配系统。 该系统通过生成模板库（每个单独的模板是三维数组，数组中的每个像素表示特定x，y和z坐标上的值）启动。 沿着一个轴（例如，z）的每列像素被转换为神经输入。 每个神经输入通过神经网络馈送，以建立每个神经输入和输出神经元之间的延迟连接并产生模板神经网络。 另外，测试图像被转换为​​神经输入。 测试图像的神经输入输入模板神经网络以产生输出神经元。 评估输出神经元以识别测试图像中模板的位置。

公开(公告)号：US09530708B1

公开(公告)日：2016-12-27

申请号：US13906750

申请日：2013-05-31

Applicant: HRL Laboratories, LLC

Inventor： Hasan Sharifi ,  Keisuke Shinohara ,  Mary C. Montes ,  Charles McGuire ,  Wonill Ha ,  Jason May ,  Hooman Kazemi ,  Jongchan Kang ,  Robert G. Nagele

IPC: H01L21/00 ,  H01L23/12 ,  H01L21/58

CPC classification number: H01L23/66 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/12 ,  H01L23/367 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/80 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2223/6672

Abstract: An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dielectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

Abstract translation: 一种电子电路，包括：集成电路芯片，所述集成电路芯片具有顶面; 芯片顶面的部分由与集成电路电连接的第一金属层覆盖; 以及在所述第一金属层的旁边和顶部形成在所述芯片的上表面上的介电层; 其中所述电介质层平行于所述芯片的所述顶面延伸超过所述芯片的边缘，所述第一金属层在所述电介质层中延伸超过所述芯片的边缘; 并且其中介电层的顶表面的部分被第二金属层覆盖，第一和第二金属层的部分通过电介质层电连接。

公开(公告)号：US10056340B1

公开(公告)日：2018-08-21

申请号：US15346155

申请日：2016-11-08

Applicant: HRL Laboratories, LLC

Inventor： Hasan Sharifi ,  Keisuke Shinohara ,  Mary C. Montes ,  Charles McGuire ,  Wonill Ha ,  Jason May ,  Hooman Kazemi ,  Jongchan Kang ,  Robert G. Nagele

IPC: H01L23/00 ,  H01L23/66 ,  H01L21/683 ,  H01L21/311 ,  H01L23/12

CPC classification number: H01L23/66 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/12 ,  H01L23/367 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/80 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2223/6672

Abstract: An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dialectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

公开(公告)号：US09252247B1

公开(公告)日：2016-02-02

申请号：US14151979

申请日：2014-01-10

Applicant: HRL Laboratories, LLC

Inventor： Miroslav Micovic ,  Andrea Corrion ,  Keisuke Shinohara ,  Peter J Willadsen ,  Shawn D Burnham ,  Hooman Kazemi ,  Paul B Hashimoto

IPC: H01L29/739 ,  H01L21/338 ,  H01L29/66

CPC classification number: H01L29/66916 ,  H01L29/0891 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7787

Abstract: The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.

Abstract translation: 通过在栅极区域之外设计2DEG的带隙，使得电荷密度显着增加，可以显着降低HFET的源极/漏极和栅极之间的界面电阻。 通过在沟道层和阻挡层上使用n + GaN帽层可以进一步降低电阻，使得超过栅极区域的势垒层的水平表面被n + GaN帽层覆盖。 该技术适用于耗尽和增强型HFET。