公开(公告)号：US10170611B1

公开(公告)日：2019-01-01

申请号：US15192942

申请日：2016-06-24

Applicant: HRL Laboratories, LLC

Inventor： Yan Tang ,  Keisuke Shinohara ,  Dean C. Regan ,  Helen Hor Ka Fung ,  Miroslav Micovic

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L27/06

Abstract: Semiconductor devices, such as transistors, FETs and HEMTs having a non-linear gate foot region and non-linear channel width are disclosed as well as methods of making and using such devices and the operational benefits of the devices.

公开(公告)号：US08980759B1

公开(公告)日：2015-03-17

申请号：US14284905

申请日：2014-05-22

Applicant: HRL Laboratories, LLC

Inventor： Andrea Corrion ,  Joel C. Wong ,  Keisuke Shinohara ,  Miroslav Micovic ,  Ivan Milosavljevic ,  Dean C. Regan ,  Yan Tang

IPC: H01L21/302 ,  H01L29/40 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/20

CPC classification number: H01L29/402 ,  H01L21/0335 ,  H01L21/28593 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of forming a slanted field plate including forming epitaxy for a FET on a substrate, forming a wall near a drain of the FET, the wall comprising a first negative tone electron-beam resist (NTEBR), depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET, depositing a second NTEBR over the dielectric, wherein surface tension causes the deposited second NTEBR to have a slanted top surface between the step and a source of the FET, etching anisotropically vertically the second NTEBR and the dielectric to remove the second NTEBR and to transfer a shape of the slanted top surface to the dielectric, and forming a gatehead comprising metal on the dielectric between the step and the source of the FET, wherein the gatehead forms a slanted field plate.

Abstract translation: 一种形成倾斜场板的方法，包括在衬底上形成用于FET的外延，在FET的漏极附近形成壁，所述壁包括第一负色调电子束抗蚀剂（NTEBR），在所述外延上沉积电介质，以及 所述壁，所述壁使所述电介质在所述FET的漏极附近具有台阶，在所述电介质上沉积第二NTEBR，其中表面张力使所沉积的第二NTEBR在所述台阶和所述FET源之间具有倾斜的顶表面 ，第二NTEBR和电介质的各向异性垂直蚀刻以去除第二NTEBR并将倾斜的顶表面的形状转移到电介质，以及在FET的台阶和源极之间的电介质上形成包含金属的栅极头，其中， 门头形成倾斜的场板。

公开(公告)号：US10998273B2

公开(公告)日：2021-05-04

申请号：US16158212

申请日：2018-10-11

Applicant: HRL Laboratories, LLC

Inventor： Florian G. Herrault ,  David Brown ,  Hasan Sharifi ,  Joel C. Wong ,  Dean C. Regan ,  Yan Tang ,  Helen Fung

IPC: H01L23/538 ,  H01L23/482 ,  H01L23/367 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/16 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L23/00

Abstract: An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said first component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip top surface; a first conductor connecting said wafer contact pad and said component contact pad.

公开(公告)号：US09449833B1

公开(公告)日：2016-09-20

申请号：US14101102

申请日：2013-12-09

Applicant: HRL LABORATORIES, LLC.

Inventor： Dean C. Regan ,  Keisuke Shinohara ,  Yan Tang ,  Miroslav Micovic

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L21/28587 ,  H01L21/28114 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7783

Abstract: A self-aligned process for locating a stem of a T-shaped gate relative to source and drain contacts of a FET or HEMT. The gate stem is located asymmetrically in some embodiments and in such embodiments the stem of the T-shaped gate is located relative to drain and source contacts of the device by forming a plurality of sidewall spacers, with more sidewall spacers being formed on the drain side of the stem than are formed on the source side of the stem. Additionally the gate stem preferably has a high aspect ratio to improve the performance of the resulting FET or HEMT. Drain and source contacts are preferably formed of an n+ semiconductor material.

Abstract translation: 用于定位T形栅极的茎相对于FET或HEMT的源极和漏极接触的自对准工艺。 门杆在一些实施例中是不对称的，并且在这种实施例中，通过形成多个侧壁间隔件，T形门的杆相对于器件的漏极和源极接触定位，在漏极侧形成更多的侧壁间隔物 的茎比在茎的源侧形成。 此外，门极优选地具有高纵横比以改善所得FET或HEMT的性能。 漏极和源极触点优选由n +半导体材料形成。

公开(公告)号：US10734498B1

公开(公告)日：2020-08-04

申请号：US16101294

申请日：2018-08-10

Applicant: HRL Laboratories, LLC

Inventor： David F. Brown ,  Jeong-Sun Moon ,  Yan Tang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L21/285 ,  H01L29/778 ,  H01L29/08

Abstract: A four-terminal GaN transistor and methods of manufacture, the transistor having source and drain regions and preferably two T-shaped gate electrodes, wherein a stem of one of the two T-shaped gate electrodes is more closely located to the source region than it is to a stem of the other one of the two T-shaped gate electrodes and wherein the stem of the other one of the two T-shaped gate electrodes is more closely located to the drain region than it is to the stem of said one of the two T-shaped gate electrodes. The the gate closer to the source region is a T-gate, and the proximity of the two gates is less than 500 nm from each other. The spacing between the stem of the RF gate and source region and the stem of the DC gate and drain region are preferably defined by self-aligned fabrication techniques. The four-terminal GaN transistor is capable of operation in the W-band (75 to 100 GHz).