公开(公告)号：US20110063085A1

公开(公告)日：2011-03-17

申请号：US12623999

申请日：2009-11-23

申请人： HYUNMIN JANG ,  Wonjun Lee ,  Donghwan Lee ,  Joosik Lee ,  Sukil Kang ,  Youngshin Yoon ,  Junghee Han

发明人： HYUNMIN JANG ,  Wonjun Lee ,  Donghwan Lee ,  Joosik Lee ,  Sukil Kang ,  Youngshin Yoon ,  Junghee Han

IPC分类号： G06K7/01

CPC分类号： H04W28/06 ,  H04W74/08

摘要： The present invention relates to a method for determining an optimal frame size for tag collision prevention in an Aloha-based RFID system in which frame sizes limited to a certain unit are used to identify tags, the method including the steps of using an RFID for: (a) calculating an estimated optimal frame value for the RFID reader identifying the tags; (b) calculating expected time delays per tag of a left-hand frame size and a right-hand frame size, which show the smallest differences with respect to the estimated optimal frame value, among the frame sizes; (c) comparing, the expected time delay per tag of the left-hand frame size with that of the right-hand frame size; and (d) determining a frame size which has a smaller expected time delay per tag, between the left-hand frame size and the right-hand frame size, to be an optimal frame size.

摘要翻译： 本发明涉及一种在基于Aloha的RFID系统中确定用于标签碰撞预防的最佳帧大小的方法，其中使用限于某个单元的帧大小来识别标签，该方法包括以下步骤： （a）计算识别标签的RFID读取器的估计最佳帧值; （b）在帧大小之间计算每个标签的左侧帧大小和右侧帧大小的预测时间延迟，其显示相对于估计的最佳帧值的最小差异; （c）将左侧帧大小的每个标签的预期时间延迟与右侧帧大小的预期时间延迟进行比较; 以及（d）确定在左侧帧大小和右侧帧大小之间具有较小的每个标签的预期时间延迟的帧大小为最佳帧大小。

公开(公告)号：US08610544B2

公开(公告)日：2013-12-17

申请号：US12623999

申请日：2009-11-23

申请人： Hyunmin Jang ,  Wonjun Lee ,  Donghwan Lee ,  Joosik Lee ,  Sukil Kang ,  Youngshin Yoon ,  Junghee Han

发明人： Hyunmin Jang ,  Wonjun Lee ,  Donghwan Lee ,  Joosik Lee ,  Sukil Kang ,  Youngshin Yoon ,  Junghee Han

IPC分类号： H04Q5/22

CPC分类号： H04W28/06 ,  H04W74/08

摘要： The present invention relates to a method for determining an optimal frame size for tag collision prevention in an Aloha-based RFID system in which frame sizes limited to a certain unit are used to identify tags, the method including the steps of using an RFID for: (a) calculating an estimated optimal frame value for the RFID reader identifying the tags; (b) calculating expected time delays per tag of a left-hand frame size and a right-hand frame size, which show the smallest differences with respect to the estimated optimal frame value, among the frame sizes; (c) comparing, the expected time delay per tag of the left-hand frame size with that of the right-hand frame size; and (d) determining a frame size which has a smaller expected time delay per tag, between the left-hand frame size and the right-hand frame size, to be an optimal frame size.

摘要翻译： 本发明涉及一种在基于Aloha的RFID系统中确定用于标签碰撞预防的最佳帧大小的方法，其中使用限于某个单元的帧大小来识别标签，该方法包括以下步骤： （a）计算识别标签的RFID读取器的估计最佳帧值; （b）在帧大小之间计算每个标签的左侧帧大小和右侧帧大小的预测时间延迟，其显示相对于估计的最佳帧值的最小差异; （c）将左侧帧大小的每个标签的预期时间延迟与右侧帧大小的预期时间延迟进行比较; 以及（d）确定在左侧帧大小和右侧帧大小之间具有较小的每个标签的预期时间延迟的帧大小为最佳帧大小。

公开(公告)号：US20110299690A1

公开(公告)日：2011-12-08

申请号：US13202690

申请日：2010-02-23

申请人： Donghwan Lee

发明人： Donghwan Lee

IPC分类号： H04R5/00

CPC分类号： G06F13/4291 ,  G06F2213/0016 ,  G10L19/008 ,  G10L19/167

摘要： A method and apparatus for transmitting audio data is disclosed. In the method of sending audio data, audio data to be sent are divided into basic channel audio data and supplementary audio data for services of a high channel. When a left channel or a right channel is selected in response to a word selection signal in accordance with the standards of a serial bus, the basic channel audio data corresponding to a selected channel are sent, and at least one of the supplementary audio data is sent during the remaining time until another channel is selected in response to the word selection signal. Accordingly, audio data of a high channel, such as a 5.1 channel, can be sent without a design change using a serial bus for supporting a 2 channel, such as an I2S bus.

摘要翻译： 公开了一种用于传输音频数据的方法和装置。 在发送音频数据的方法中，要发送的音频数据被划分成用于高频道服务的基本频道音频数据和辅助音频数据。 当根据串行总线的标准响应于字选择信号选择左声道或右声道时，发送与所选频道相对应的基本声道音频数据，并且至少一个辅助音频数据是 在剩余时间内发送，直到响应于字选择信号选择了另一个频道。 因此，可以使用用于支持诸如I2S总线的2通道的串行总线来发送诸如5.1通道的高通道的音频数据而不进行设计改变。

公开(公告)号：US20110215851A1

公开(公告)日：2011-09-08

申请号：US13033057

申请日：2011-02-23

申请人： Ji Hun OH ,  Donghwan Lee

发明人： Ji Hun OH ,  Donghwan Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/06

摘要： Provided are a delay locked loop (DLL), which is capable of being adopted at a data processing system and include a duty correction circuit, and a duty correction method at the DLL. The duty correction method includes generating first and second delay clock signals having different phase shifts by delaying an external clock signal by as much as first and second set phases in response to a delay control signal, generating first and second first signals respectively synchronized with the first and second delay clock signals, and generating an output clock signal having a set duty ratio by using the first and second pulse signals. According to the foregoing, a more accurate duty correction operation is performed without a half cycle time delay line or a matching delay line.

摘要翻译： 提供了一种延迟锁定环（DLL），其能够在数据处理系统中被采用，并且包括占空比校正电路和DLL处的占空比校正方法。 占空比校正方法包括响应于延迟控制信号，通过将外部时钟信号延迟多达第一和第二设定相位而产生具有不同相移的第一和第二延迟时钟信号，产生分别与第一和第二设定相位同步的第一和第二第一信号 和第二延迟时钟信号，并且通过使用第一和第二脉冲信号产生具有设定占空比的输出时钟信号。 根据上述，在没有半周期时间延迟线或匹配延迟线的情况下执行更精确的占空比校正操作。

公开(公告)号：US20180067697A1

公开(公告)日：2018-03-08

申请号：US15605404

申请日：2017-05-25

申请人： Donghwan Lee ,  Junjin Kong ,  Seongnam Kwon ,  Seungkyung Ro ,  Changkyu Seol ,  Hong Rak Son ,  Pilsang Yoon ,  Donggi Lee ,  Heewon Lee

发明人： Donghwan Lee ,  Junjin Kong ,  Seongnam Kwon ,  Seungkyung Ro ,  Changkyu Seol ,  Hong Rak Son ,  Pilsang Yoon ,  Donggi Lee ,  Heewon Lee

IPC分类号： G06F3/06 ,  G06N99/00

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06N99/005 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

摘要： A storage device may include a nonvolatile memory device, a buffer memory, and a controller. The controller may perform first accesses on the nonvolatile memory device using the buffer memory, collect access result information and access environment information of the first accesses in the buffer memory, and generate an access classifier that predicts a result of a second access to the nonvolatile memory device by performing machine learning based on the access result information and the access environment information collected in the buffer memory.

公开(公告)号：US20110221495A1

公开(公告)日：2011-09-15

申请号：US13046073

申请日：2011-03-11

申请人： Won LEE ,  Donghwan Lee ,  Seong-Ook Jung ,  Heechai Kang ,  Kyungho Ryu ,  Donghoon Jung

发明人： Won LEE ,  Donghwan Lee ,  Seong-Ook Jung ,  Heechai Kang ,  Kyungho Ryu ,  Donghoon Jung

IPC分类号： H03L7/06 ,  H03K5/156

CPC分类号： H03K5/1565 ,  G11C7/222 ,  H03L7/0814

摘要： Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.

摘要翻译： 提供了可以包括在数据处理装置中的延迟锁定环（DLL），并且可以包括这样的DLL的占空比校正电路和占空比校正方法。 占空比校正方法包括：在时钟的第一次转换时对输出时钟进行二次转换，对输出时钟的第一次转换进行占空比校正的时钟采样，以检测占空比的误差，并执行占空比 根据检测到的占空比误差，使用偏斜栅极链进行校正。

公开(公告)号：US10013211B2

公开(公告)日：2018-07-03

申请号：US15605404

申请日：2017-05-25

申请人： Donghwan Lee ,  Junjin Kong ,  Seongnam Kwon ,  Seungkyung Ro ,  Changkyu Seol ,  Hong Rak Son ,  Pilsang Yoon ,  Donggi Lee ,  Heewon Lee

发明人： Donghwan Lee ,  Junjin Kong ,  Seongnam Kwon ,  Seungkyung Ro ,  Changkyu Seol ,  Hong Rak Son ,  Pilsang Yoon ,  Donggi Lee ,  Heewon Lee

IPC分类号： G11C7/00 ,  G06F3/06 ,  G06N99/00

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06N20/00 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

摘要： A storage device may include a nonvolatile memory device, a buffer memory, and a controller. The controller may perform first accesses on the nonvolatile memory device using the buffer memory, collect access result information and access environment information of the first accesses in the buffer memory, and generate an access classifier that predicts a result of a second access to the nonvolatile memory device by performing machine learning based on the access result information and the access environment information collected in the buffer memory.

公开(公告)号：US08519758B2

公开(公告)日：2013-08-27

申请号：US13046073

申请日：2011-03-11

申请人： Won Lee ,  Donghwan Lee ,  Seong-Ook Jung ,  Heechai Kang ,  Kyungho Ryu ,  Donghoon Jung

发明人： Won Lee ,  Donghwan Lee ,  Seong-Ook Jung ,  Heechai Kang ,  Kyungho Ryu ,  Donghoon Jung

IPC分类号： H03L7/06 ,  H03K5/04

CPC分类号： H03K5/1565 ,  G11C7/222 ,  H03L7/0814

摘要： Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.

摘要翻译： 提供了可以包括在数据处理装置中的延迟锁定环（DLL），并且可以包括这样的DLL的占空比校正电路和占空比校正方法。 占空比校正方法包括：在时钟的第一次转换时对输出时钟进行二次转换，对输出时钟的第一次转换进行占空比校正的时钟采样，以检测占空比的误差，并执行占空比 根据检测到的占空比误差，使用偏斜栅极链进行校正。

公开(公告)号：US08536914B2

公开(公告)日：2013-09-17

申请号：US13033057

申请日：2011-02-23

申请人： Ji Hun Oh ,  Donghwan Lee

发明人： Ji Hun Oh ,  Donghwan Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/06

摘要： Provided are a delay locked loop (DLL), which is capable of being adopted at a data processing system and include a duty correction circuit, and a duty correction method at the DLL. The duty correction method includes generating first and second delay clock signals having different phase shifts by delaying an external clock signal by as much as first and second set phases in response to a delay control signal, generating first and second first signals respectively synchronized with the first and second delay clock signals, and generating an output clock signal having a set duty ratio by using the first and second pulse signals. According to the foregoing, a more accurate duty correction operation is performed without a half cycle time delay line or a matching delay line.

摘要翻译： 提供了一种延迟锁定环（DLL），其能够在数据处理系统中被采用，并且包括在DLL处的占空比校正电路和占空比校正方法。 占空比校正方法包括响应于延迟控制信号，通过将外部时钟信号延迟多达第一和第二设定相位而产生具有不同相移的第一和第二延迟时钟信号，产生分别与第一和第二设定相位同步的第一和第二第一信号 和第二延迟时钟信号，并且通过使用第一和第二脉冲信号产生具有设定占空比的输出时钟信号。 根据上述，在没有半周期时间延迟线或匹配延迟线的情况下执行更精确的占空比校正操作。