-
1.发明申请Clock and Data Recovery Employing Piece-Wise Estimation on the Derivative of the Frequency 有权时钟和数据恢复采用对频率微分的智慧估计公开(公告)号：US20130136220A1
公开(公告)日：2013-05-30
申请号：US13674812
申请日：2012-11-12
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.
摘要翻译： 一种用于执行时钟和数据恢复的系统和方法。 根据数据发送器时钟的频率和接收机时钟的频率之间的偏移的变化率的至少三个估计，系统设置恢复的时钟信号的相位。
-
2.发明申请CLOCK AND DATA RECOVERY EMPLOYING PIECE-WISE ESTIMATION ON THE DERIVATIVE OF THE FREQUENCY 有权时钟和数据恢复在频率的衍生中使用一个简单的估计公开(公告)号：US20100090732A1
公开(公告)日：2010-04-15
申请号：US12441003
申请日：2007-09-05
IPC分类号： H03L7/00
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.
摘要翻译： 一种用于执行时钟数据恢复的系统和方法。 系统根据数据发送器时钟的频率和接收机时钟15的频率之间的偏移的变化率的至少三个估计来设置恢复的时钟信号30的相位。
-
3.发明授权Clock and data recovery employing piece-wise estimation on the derivative of the frequency 有权使用对频率导数进行分段估计的时钟和数据恢复公开(公告)号：US08311176B2
公开(公告)日：2012-11-13
申请号：US12441003
申请日：2007-09-05
IPC分类号： H03D3/24
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.
摘要翻译： 一种用于执行时钟和数据恢复的系统和方法。 系统根据数据发送器时钟的频率和接收机时钟15的频率之间的偏移的变化率的至少三个估计来设置恢复的时钟信号30的相位。
-
公开(公告)号：US09141479B2
公开(公告)日：2015-09-22
申请号：US12940942
申请日：2010-11-05
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译： 存储器系统包括具有至少一个信号线的链路和控制器。 所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。 第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。 至少一个接收器耦合到链路以接收第二数据。 第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。 该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。 耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。
-
公开(公告)号：US08634452B2
公开(公告)日：2014-01-21
申请号：US13491508
申请日：2012-06-07
申请人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
IPC分类号： H04B17/00
CPC分类号： H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要： An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.
摘要翻译： 集成电路装置包括：第一电路，用于接收与电输入信号的第一数据周期相关联的位，可操作以产生关于与第一数据周期相关联的位的逻辑状态的判定;以及第二电路，用于接收与第 电输入信号的第二周期，以产生关于与第二数据周期相关联的位的逻辑状态的判定。 均衡电路根据第一电路的输出补偿影响第二电路的符号间干扰，并根据第一电路以外的电路的输出补偿影响第一电路的符号间干扰，该电路可操作以产生关于位的逻辑状态的判定 的电气输入信号。
-
公开(公告)号：US08564328B2
公开(公告)日：2013-10-22
申请号：US13476247
申请日：2012-05-21
申请人： Vladimir M. Stojanovic , Andrew C. C. Ho , Anthony Bessios , Fred F. Chen , Elad Alon , Mark A. Horowitz
发明人： Vladimir M. Stojanovic , Andrew C. C. Ho , Anthony Bessios , Fred F. Chen , Elad Alon , Mark A. Horowitz
IPC分类号： H03K19/0175
CPC分类号： H04L25/49 , H04B1/04 , H04B1/0475 , H04B2001/0416 , H04L25/025 , H04L25/028 , H04L25/0282 , H04L25/03019 , H04L25/03343 , H04L25/03885 , H04L25/061 , H04L25/4917 , H04L2025/03363 , H04L2025/03802
摘要： A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.
-
公开(公告)号：US20100296566A1
公开(公告)日：2010-11-25
申请号：US12596133
申请日：2008-01-30
IPC分类号： H04B17/00
CPC分类号： G01R31/31708 , G01R31/3171 , G01R31/318342
摘要： Embodiments of a system for determining and optimizing the performance a signaling system are described. During operation, the system captures or measures a single-bit response (SBR) for the signaling system. Next, the system constructs an idealized inter-symbol-interference-free (ISI-free) SBR for the signaling system which is substantially free of inter-symbol-interference (ISI). The system then calculates an ISI-residual from the captured SBR and the idealized ISI-free SBR. Next, the system constructs a calibration bit pattern for the signaling system that is based substantially on the ISI-residual. Finally, the system uses the calibration bit pattern to calibrate, optimize and determine an aspect of the performance of the signaling system.
摘要翻译： 描述了用于确定和优化信号系统的性能的系统的实施例。 在操作期间，系统捕获或测量信令系统的单位响应（SBR）。 接下来，该系统为基本上没有符号间干扰（ISI）的信令系统构建理想化的符号间无干扰（ISI-free）SBR。 然后系统从捕获的SBR和理想的无ISI的SBR计算ISI残差。 接下来，系统构建用于基本上基于ISI残差的信令系统的校准位模式。 最后，系统使用校准位模式来校准，优化和确定信号系统性能的一个方面。
-
公开(公告)号：US07723662B2
公开(公告)日：2010-05-25
申请号：US12089371
申请日：2006-10-06
申请人： Marc S. Levoy , Yi-Ren Ng , Mark A. Horowitz
发明人： Marc S. Levoy , Yi-Ren Ng , Mark A. Horowitz
IPC分类号： H01L27/00
CPC分类号： G02B21/361 , G02B21/367 , G02B27/0075
摘要： Light-field microscopy is facilitated using an approach to image computation. In connection with an example embodiment, a subject (e.g., 105) is imaged by passing light from the subject through a microlens array (e.g., 120) to a photosensor array (e.g., 130) to simultaneously detect light from the subject that is passed through different directions to different locations. In certain embodiments, information from the detected light is used to compute refocused images, perspective images and/or volumetric datasets, from a single-shot photograph.
摘要翻译： 使用图像计算的方法来促进光场显微镜。 结合示例实施例，通过将来自受试者的光通过微透镜阵列（例如，120）传递到光电传感器阵列（例如，130）来对被摄体（例如，105）进行成像，以同时检测来自被摄体的光 通过不同的方向到不同的位置。 在某些实施例中，来自检测到的光的信息用于从单次照片计算重聚焦图像，透视图像和/或体积数据集。
-
公开(公告)号：US20100117706A1
公开(公告)日：2010-05-13
申请号：US12693285
申请日：2010-01-25
申请人： Vladimir M. Stojanovic , Andrew C. C. Ho , Anthony Bessios , Fred F. Chen , Elad Alon , Mark A. Horowitz
发明人： Vladimir M. Stojanovic , Andrew C. C. Ho , Anthony Bessios , Fred F. Chen , Elad Alon , Mark A. Horowitz
IPC分类号： H03L5/00
CPC分类号： H04L25/49 , H04B1/04 , H04B1/0475 , H04B2001/0416 , H04L25/025 , H04L25/028 , H04L25/0282 , H04L25/03019 , H04L25/03343 , H04L25/03885 , H04L25/061 , H04L25/4917 , H04L2025/03363 , H04L2025/03802
摘要： A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.
摘要翻译： 具有自适应发送预加重的高速信号系统。 发射电路具有多个输出驱动器，以将第一信号输出到信号路径上。 接收电路被耦合以经由信号路径接收第一信号并被配置为生成第一信号是否超过阈值电平的指示。 第一阈值控制电路被耦合以从接收电路接收指示，并且被配置为根据第一信号是否超过阈值电平来调整阈值电平。 驱动强度控制电路被耦合以从接收电路接收指示，并且被配置为根据第一信号是否超过阈值电平来调整多个输出驱动器中的至少一个输出驱动器的驱动强度。
-
公开(公告)号：US07715509B2
公开(公告)日：2010-05-11
申请号：US12403340
申请日：2009-03-12
申请人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
发明人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
IPC分类号： H04L7/00
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.
-
-
-
-
-
-
-
-
-
搜索结果
133 条记录 (耗时 0.04 秒)
