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    Method of forming a tantalum carbon nitride layer and method of manufacturing a semiconductor device using the same
    6.
    发明申请
    Method of forming a tantalum carbon nitride layer and method of manufacturing a semiconductor device using the same 审中-公开
    形成钽碳氮化物层的方法和使用其制造半导体器件的方法

    公开(公告)号：US20070059929A1

    公开(公告)日：2007-03-15

    申请号：US11438941

    申请日：2006-05-23

    申请人： Hag-Ju Cho ,  Sang-Bom Kang ,  Seong-Geon Park ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin

    发明人： Hag-Ju Cho ,  Sang-Bom Kang ,  Seong-Geon Park ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28556 ,  C23C16/36 ,  H01L21/28088 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10888 ,  H01L29/4966 ,  H01L29/66583

    摘要： In some embodiments of the present invention, methods of forming a tantalum carbon nitride layer include introducing a source gas including a tantalum metal complex onto a substrate, wherein one or more of the ligands of the tantalum metal complex include nitrogen and one or more of the ligands of the tantalum metal complex include carbon; and thermally decomposing the tantalum metal complex to form a tantalum carbon nitride layer on the substrate. In some embodiments, the tantalum metal complex includes Ta(NR1)(NR2R3)3, wherein R1, R2 and R3 are each independently H or a C1-C6 alkyl group. In some embodiments, the tantalum metal complex may be [Ta(═NC(CH3)2C2H5)(N(CH3)2)3]. Methods of forming a gate structure, methods of manufacturing dual gate electrodes and methods of manufacturing a capacitor including tantalum carbon nitride are also provided herein.

    摘要翻译： 在本发明的一些实施例中，形成氮化钽层的方法包括将包含钽金属络合物的源气体引入到基底上，其中一个或多个钽金属络合物的配体包括氮和一个或多个 钽金属络合物的配体包括碳; 并且在所述衬底上热分解所述钽金属络合物以形成钽碳氮化物层。 在一些实施方案中，钽金属络合物包括Ta（NR 1）3（NR 2 R 3）3， 其中R 1，R 2和R 3各自独立地为H或C 1 -C 3 - 6烷基。 在一些实施方案中，钽金属络合物可以是[Ta（-NC（CH 3）2）2 H 2 H 5， （N（CH 3）2）3）3。 形成栅极结构的方法，制造双栅电极的方法以及制造包括氮化钽的电容器的方法也在本文中提供。

    Method of manufacturing a semiconductor device having a tungsten carbon nitride layer
    7.
    发明申请
    Method of manufacturing a semiconductor device having a tungsten carbon nitride layer 审中-公开
    制造具有碳化钨层的半导体器件的方法

    公开(公告)号：US20070128775A1

    公开(公告)日：2007-06-07

    申请号：US11607600

    申请日：2006-12-01

    申请人： Taek-Soo Jeon ,  Hag-ju Cho ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

    发明人： Taek-Soo Jeon ,  Hag-ju Cho ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

    IPC分类号： H01L21/84

    CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

    摘要： A method of manufacturing a gate electrode of a MOS transistor including a tungsten carbon nitride layer is disclosed. After a high dielectric layer is formed on a substrate, a source gas including tungsten amine derivative flows onto the high dielectric layer. A tungsten carbon nitride layer is formed on the high dielectric layer by decomposing the source gas. Thereafter, a gate electrode is formed by patterning the tungsten carbon nitride layer. According to the present invention, a gate electrode having a work function of over 4.9 eV is formed.

    摘要翻译： 公开了一种制造包括氮化钨层的MOS晶体管的栅电极的方法。 在基板上形成高电介质层之后，包含钨胺衍生物的源气体流到高电介质层上。 通过分解源气体，在高电介质层上形成碳氮化钨层。 此后，通过图案化氮化碳钨层来形成栅电极。 根据本发明，形成功函数为4.9eV以上的栅电极。

    Semiconductor device with dual gates and method of manufacturing the same
    8.
    发明申请
    Semiconductor device with dual gates and method of manufacturing the same 有权
    具有双门的半导体器件及其制造方法

    公开(公告)号：US20070111453A1

    公开(公告)日：2007-05-17

    申请号：US11497998

    申请日：2006-08-01

    申请人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

    发明人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

    IPC分类号： H01L21/336 ,  H01L29/94

    CPC分类号： H01L21/823842

    摘要： In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

    摘要翻译： 在具有双栅极的半导体器件及其制造方法中，在具有第一和第二区域的半导体衬底上依次形成电介质层和第一和第二金属导电层。 形成在第二区域的第一金属导电层上的第二金属导电层被蚀刻以形成金属图案。 使用金属图案作为蚀刻掩模蚀刻第一金属导电层。 在电介质层和金属图案上形成多晶硅层。 第一栅极通过蚀刻第一区域的多晶硅层，金属图案和第一金属导电层的部分而形成。 通过蚀刻直接形成在第二区域的电介质层上的多晶硅层的一部分来形成第二栅电极。

    Method of manufacturing a semiconductor device having a dual gate structure
    9.
    发明申请
    Method of manufacturing a semiconductor device having a dual gate structure 有权
    制造具有双栅结构的半导体器件的方法

    公开(公告)号：US20070082415A1

    公开(公告)日：2007-04-12

    申请号：US11497972

    申请日：2006-08-01

    申请人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Sang-Yong Kim

    发明人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Sang-Yong Kim

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

    摘要： A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.

    摘要翻译： 具有双栅极的半导体器件形成在具有电介质层的衬底上。 在电介质层上形成第一金属导电层至第一厚度，并且退火以降低蚀刻速率。 在第一金属导电层上形成第二金属导电层至大于第一厚度的第二厚度。 使用蚀刻选择性去除在衬底的第二区域中形成的第二金属导电层的一部分。 具有包括第一和第二金属导电层的第一金属栅极的第一栅极结构形成在衬底的第一区域中。 具有第二金属栅极的第二栅极结构形成在第二区域中。 由于第一金属导电层，栅极电介质层不暴露于蚀刻化学品，因此其介电特性不劣化。

    Gate electrode structure and method of forming the same, and semiconductor transistor having the gate electrode structure and method of manufacturing the same
    10.
    发明申请
    Gate electrode structure and method of forming the same, and semiconductor transistor having the gate electrode structure and method of manufacturing the same 审中-公开
    栅电极结构及其形成方法，以及具有栅电极结构的半导体晶体管及其制造方法

    公开(公告)号：US20070026596A1

    公开(公告)日：2007-02-01

    申请号：US11492400

    申请日：2006-07-25

    申请人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

    发明人： Hag-Ju Cho ,  Taek-Soo Jeon ,  Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823828 ,  H01L21/823835 ,  H01L21/823842

    摘要： In a gate structure and a method of forming the same, a first conductive pattern is formed on a substrate and comprises a metal-containing material. A second conductive pattern is formed on the first conductive pattern, and the second conductive pattern comprises metal and silicon. A third conductive pattern is formed on the second conductive pattern, and the third conductive pattern comprises polysilicon. A gate conductive pattern of an n-type metal-oxide semiconductor (NMOS) transistor, a p-type MOS (PMOS) transistor and a complementary MOS (CMOS) transistor includes the gate structure. The second conductive pattern is interposed between the first and third conductive patterns and the third conductive pattern is prevented from making direct contact with the first conductive pattern, so that polysilicon in the third conductive pattern is sufficiently prevented from being chemically reacted with the metal in the first conductive pattern in advance, thereby improving electrical characteristics of the transistor.

    摘要翻译： 在栅极结构及其形成方法中，第一导电图案形成在基板上并且包括含金属的材料。 在第一导电图案上形成第二导电图案，并且第二导电图案包括金属和硅。 在第二导电图案上形成第三导电图案，并且第三导电图案包括多晶硅。 n型金属氧化物半导体（NMOS）晶体管，p型MOS（PMOS）晶体管和互补MOS（CMOS）晶体管的栅极导电图案包括栅极结构。 第二导电图案插入在第一和第三导电图案之间，并且防止第三导电图案与第一导电图案直接接触，使得充分防止第三导电图案中的多晶硅与金属在化学反应中 第一导电图案，从而改善晶体管的电特性。