公开(公告)号：US20060099793A1

公开(公告)日：2006-05-11

申请号：US10904059

申请日：2004-10-21

申请人： Haining Yang ,  Clement Wann ,  Huilong Zhu

发明人： Haining Yang ,  Clement Wann ,  Huilong Zhu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7842 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure is provided which includes a semiconductor device region including a first portion and a second portion. A current-conducting member is provided, which extends horizontally over the first portion but not over the second portion. A first film, such as a stress-imparting film, extends over the second portion and only partially over the current-conducting member to expose a contact portion of the member. A first contact via is provided in conductive communication with the contact portion of the member, the first contact via having a self-aligned silicide-containing region. A second contact via is provided in conductive communication with the second portion of the semiconductor device region, the second contact via extending through the first film.

摘要翻译： 提供一种结构，其包括包括第一部分和第二部分的半导体器件区域。 提供导电构件，其在第一部分上水平延伸，但不在第二部分上。 诸如应力赋予膜的第一膜在第二部分上延伸并且仅部分地在导电构件上方以暴露构件的接触部分。 第一接触通孔设置成与构件的接触部分导电连通，第一接触通孔具有自对准的含硅化物区域。 第二接触通孔设置成与半导体器件区域的第二部分导电连通，第二接触通孔延伸穿过第一膜。

公开(公告)号：US20060261477A1

公开(公告)日：2006-11-23

申请号：US11492456

申请日：2006-07-25

申请人： Haining Yang ,  Clement Wann ,  Huilong Zhu

发明人： Haining Yang ,  Clement Wann ,  Huilong Zhu

IPC分类号： H01L23/48

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7842 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided of forming a contact to a semiconductor structure. A current-conducting member is formed which extends horizontally over a first portion of a semiconductor device region but not over a second portion of such semiconductor device region. A first film is formed which extends over the second portion and only partially over the member to expose a contact portion of the member. A first contact via is formed in conductive communication with the contact portion. The first contact via has a silicide-containing region self-aligned to an area of the member contacted by the contact via. A second contact via is formed in conductive communication with the second portion, the second contact via extending through the first film.

摘要翻译： 提供了形成与半导体结构的接触的方法。 形成导电构件，其在半导体器件区域的第一部分上水平延伸，但不在该半导体器件区域的第二部分上。 形成第一膜，其在第二部分上延伸并且仅部分地覆盖在构件上以暴露构件的接触部分。 第一接触通孔形成为与接触部分导电连通。 第一接触通孔具有与接触通孔接触的部件的区域自对准的含硅化物区域。 第二接触通孔形成为与第二部分导电连通，第二接触通孔延伸穿过第一膜。

公开(公告)号：US20050285202A1

公开(公告)日：2005-12-29

申请号：US10710184

申请日：2004-06-24

申请人： Shih-Fen Huang ,  Clement Wann ,  Haining Yang

发明人： Shih-Fen Huang ,  Clement Wann ,  Haining Yang

IPC分类号： H01L21/338 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L29/7842 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7843

摘要： An SRAM in a CMOS integrated circuit is subjected to stress on the channels of its transistors; compressive stress on the pull-up and pass gate transistors and tensile stress on the pull-down transistors in a version designed to improve stability; and compressive stress on the pull-up transistors and tensile stress on the pull-down and pass gate transistors in a version designed to reduce the cell size and increase speed of operation.

摘要翻译： CMOS集成电路中的SRAM在其晶体管的沟道上受到应力; 上拉和栅极晶体管中的压应力和下拉晶体管中的拉伸应力，旨在提高稳定性; 并且上拉晶体管中的压应力和下拉和通过栅极晶体管中的拉伸应力在设计成减小电池尺寸并增加操作速度的版本中。

公开(公告)号：US20070259489A1

公开(公告)日：2007-11-08

申请号：US11879065

申请日：2007-07-16

申请人： Haining Yang ,  Huilong Zhu

发明人： Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78654

摘要： A method of fabrication is provided in which a field effect transistor (FET) is formed having a channel region and source and drain regions adjacent to the channel region. A first stressed region underlies the channel region, in which the first type of stress is either compressive type or tensile type. Second stressed regions having a second type of stress underlie the source and drain regions, in which the second type of stress is an opposite one of the compressive type or tensile type stress of the first stressed region.

摘要翻译： 提供一种制造方法，其中形成具有沟道区的场效应晶体管（FET）以及与沟道区相邻的源极和漏极区。 第一应力区域位于通道区域的下面，其中第一类型的应力是压缩型或拉伸型。 具有第二类型应力的第二应力区域位于源极和漏极区域之下，其中第二类型的应力是与第一应力区域的压缩类型或拉伸应力相反的一个。

公开(公告)号：US20060172500A1

公开(公告)日：2006-08-03

申请号：US10906054

申请日：2005-02-01

申请人： Haining Yang ,  Huilong Zhu

发明人： Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66477 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846 ,  Y10S257/90

摘要： A semiconductor device is provided with a stressed channel region, where the stresses film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surround the channel region, and may apply stress from all sides of the channel. Consequently, the stress film better surrounds the channel region of the semiconductor device and can apply more stress in the channel region.

摘要翻译： 半导体器件设置有应力沟道区域，其中引起应力沟道区域中的应力的应力膜可以部分地或全部地延伸在半导体器件的栅极结构之下。 在一些实施例中，应力膜环围绕通道区域，并且可以施加来自通道的所有侧面的应力。 因此，应力膜更好地围绕半导体器件的沟道区域并且可以在沟道区域中施加更多的应力。

公开(公告)号：US20060151833A1

公开(公告)日：2006-07-13

申请号：US10905586

申请日：2005-01-12

申请人： Haining Yang ,  Huilong Zhu

发明人： Haining Yang ,  Huilong Zhu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L27/0922 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78654

摘要： An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of stress is provided to underlie the channel region, in which the first type of stress is either compressive type or tensile type. Second stressed regions having a second type of stress are provided to underlie the source and drain regions, in which the second type of stress is an opposite one of the compressive type or tensile type stress of the first stressed region.

摘要翻译： 提供一种集成电路和制造方法，其中集成电路包括具有沟道区的场效应晶体管（FET）和与沟道区相邻的源极和漏极区。 提供具有第一类型应力的第一应力区域作为通道区域的下面，其中第一类型的应力是压缩型或拉伸型。 第二应力区域具有第二类型的应力，位于源区和漏区之下，其中第二类应力是与第一应力区的压缩类型或拉伸应力相反的一个。

公开(公告)号：US20050093030A1

公开(公告)日：2005-05-05

申请号：US10695748

申请日：2003-10-30

申请人： Bruce Doris ,  Haining Yang ,  Huilong Zhu

发明人： Bruce Doris ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7843

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

摘要翻译： 在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率， 取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。 因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

公开(公告)号：US20080224231A1

公开(公告)日：2008-09-18

申请号：US12105298

申请日：2008-04-18

申请人： Huilong Zhu ,  Haining Yang ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haining Yang ,  Zhijiong Luo

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L21/76816 ,  H01L21/84 ,  H01L23/485 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636

摘要： A semiconductor structure. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and a second source/drain regions. The channel region is disposed between the first and second source/drain regions and directly beneath and electrically insulated from the gate electrode region. The semiconductor structure further includes (d) a first and a second electrically conducting regions, and (e) a first and a second contact regions. The first electrically conducting region and the first source/drain region are in direct physical contact with each other at a first and a second common surfaces. The first and second common surfaces are not coplanar. The first contact region overlaps both the first and second common surfaces.

摘要翻译： 半导体结构。 半导体结构包括（a）半导体层，（b）栅极电介质区域和（c）栅电极区域。 栅电极区域与半导体层电绝缘。 半导体层包括沟道区，第一和第二源极/漏极区。 沟道区域设置在第一和第二源极/漏极区域之间，并且直接位于栅电极区域下方并与栅电极区域电绝缘。 半导体结构还包括（d）第一和第二导电区域，以及（e）第一和第二接触区域。 第一导电区域和第一源极/漏极区域在第一和第二共同表面处彼此直接物理接触。 第一和第二公共表面不共面。 第一接触区域与第一和第二公共表面重叠。

公开(公告)号：US07309901B2

公开(公告)日：2007-12-18

申请号：US10908087

申请日：2005-04-27

申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8232

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。 形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触 区域和第二S / D扩展区域。 对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。 类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

公开(公告)号：US08497168B2

公开(公告)日：2013-07-30

申请号：US13071940

申请日：2011-03-25

申请人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

发明人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/335 ,  H01L21/8232

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7843

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

摘要翻译： 在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率， 取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。 因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。