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公开(公告)号：US20100029228A1
公开(公告)日：2010-02-04
申请号：US12520518
申请日：2007-12-20
申请人： Alan Holden , Hamid Safiri , Michel J.G.J.P. Frechette , Sherif H.K. Embabi , Abdellatif Bellaouar , Stephen Arnold Devison , Tajinder Manku
发明人： Alan Holden , Hamid Safiri , Michel J.G.J.P. Frechette , Sherif H.K. Embabi , Abdellatif Bellaouar , Stephen Arnold Devison , Tajinder Manku
IPC分类号： H04B1/04
CPC分类号： H03G3/3047
摘要： A power ramping circuit for use in the transmit path of a radio frequency (RF) circuit. The power ramping circuit includes parallel connected transistors used as logarithmic resistor attenuators for adjusting current to a mixer circuit in the transmit path. The parallel connected transistors can be sized differently, and are sequentially turned off to gradually increase the current provided to the mixer circuit. A ramp control circuit controls the parallel connected transistors in response to either an analog signal or a digital signal.
摘要翻译： 一种用于射频（RF）电路的发射路径的功率斜坡电路。 功率斜坡电路包括并联的晶体管，用作对数电阻衰减器，用于调节到发射路径中的混频器电路的电流。 并联连接的晶体管的尺寸可以不同，并被依次关闭，以逐渐增加提供给混频器电路的电流。 斜坡控制电路响应于模拟信号或数字信号来控制并联的晶体管。
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公开(公告)号：US20080182537A1
公开(公告)日：2008-07-31
申请号：US11626964
申请日：2007-01-25
IPC分类号： H04B17/00
CPC分类号： H04B1/12 , H03D2200/0045 , H04B17/21
摘要： An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.
摘要翻译： 公开了一种用于无线收发器的综合自动IIP2校准架构。 该架构使得无线收发器能够生成具有最小附加电路的具有二阶音调的测试射频（RF）信号。 特别地，使用本机收发器电路和测试适配器电路的组合产生测试RF信号。 本地收发器电路是在收发器芯片上实现的用于在正常操作期间执行本机收发器功能的那些电路，其可用于产生测试（RF）信号。 测试适配器电路被添加到收发器芯片中，更具体地被添加到本地电路，用于使得本机电路能够以自测试操作模式生成测试RF信号。 用于实现特定的IIP2最小化方案的电路可以在自检操作模式下在收发器芯片中包括在自动IIP2校准中。
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公开(公告)号：US07742747B2
公开(公告)日：2010-06-22
申请号：US11626964
申请日：2007-01-25
CPC分类号： H04B1/12 , H03D2200/0045 , H04B17/21
摘要： An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.
摘要翻译： 公开了一种用于无线收发器的综合自动IIP2校准架构。 该架构使得无线收发器能够生成具有最小附加电路的具有二阶音调的测试射频（RF）信号。 特别地，使用本机收发器电路和测试适配器电路的组合产生测试RF信号。 本地收发器电路是在收发器芯片上实现的用于在正常操作期间执行本机收发器功能的那些电路，其可用于产生测试（RF）信号。 测试适配器电路被添加到收发器芯片中，更具体地被添加到本地电路，用于使得本机电路能够以自测试操作模式生成测试RF信号。 用于实现特定的IIP2最小化方案的电路可以在自检操作模式下在收发器芯片中包括在自动IIP2校准中。
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4.发明申请公开(公告)号：US20050070238A1
公开(公告)日：2005-03-31
申请号：US10833908
申请日：2004-04-28
申请人： Abdellatif Bellaouar , Alan Holden , Sher Fang
发明人： Abdellatif Bellaouar , Alan Holden , Sher Fang
CPC分类号： H04B1/30 , H04B1/0475
摘要： Methods and apparatus for reducing the amount of leakage in a transmitter are disclosed. In one embodiment, a wireless transmitter is comprises: a divider providing a local oscillation (LO) signal, a plurality of mixers that receive the LO signal and receive a signal to be modulated, a summer coupled to the plurality of mixers, and a plurality of amplifiers serially coupled to the summer. The divider couples to a capacitor, a resistor, and a power supply and the resistor and the capacitor form a pole that attenuates the LO signal present on the power supply.
摘要翻译： 公开了减少发射机泄漏量的方法和装置。 在一个实施例中，无线发射机包括：提供本地振荡（LO）信号的分频器，接收所述LO信号并接收待调制的信号的多个混频器，耦合到所述多个混频器的加法器，以及多个 的放大器串联耦合到夏天。 分压器耦合到电容器，电阻器和电源，电阻器和电容器形成一个极点，可以衰减电源上存在的LO信号。
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5.发明申请System for reducing second order intermodulation products from differential circuits 有权用于从差分电路减少二阶互调产物的系统公开(公告)号：US20070132500A1
公开(公告)日：2007-06-14
申请号：US11298667
申请日：2005-12-12
IPC分类号： G06F7/44
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D7/1466 , H03D2200/0047 , H03D2200/0088
摘要： A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated. The switching transistors of the mixer circuit can be maintained at minimal dimensions to reduce switching signal drive loading, resulting in lower power consumption and higher operating frequencies than if larger switching transistors were used.
摘要翻译： 一种具有用于平衡两个输出路径的电气特性的失配校正电路的无源CMOS差分混频器电路。 一旦差分电路的输出路径平衡或尽可能匹配，可以抑制二阶互调乘积的产生或至少降低到可接受的水平。 失配校正电路接收数字偏移信号，并产生一个或多个电压信号以选择性地施加到无源差分混频器电路的信号路径。 电压信号可以调节施加到所选晶体管的体积端子的反向栅极偏置电压以调整其阈值电压，或者可以将电压信号调整为直接施加到选定信号路径的共模电压。 由于差分混频器电路是无源的，所以不产生直流电流对噪声的贡献。 混合电路的开关晶体管可以维持在最小的尺寸以减少开关信号驱动负载，导致比使用更大的开关晶体管时更低的功耗和更高的工作频率。
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公开(公告)号：US20070223615A1
公开(公告)日：2007-09-27
申请号：US11387925
申请日：2006-03-24
申请人： Sathwant Dosanjh , Tajinder Manku , Alan Holden
发明人： Sathwant Dosanjh , Tajinder Manku , Alan Holden
CPC分类号： H04B1/50 , H04B1/0057
摘要： A transceiver interface architecture where the same RF transceiver can be used in wireless devices that support any number of standards, with or without receive diversity implementation. Each input port of the RF transceiver can be shared by a number of input signals, which effectively expands the number of available input ports. Input port sharing can be realized with virtual ports that receive two or more input signals and selectively pass one signal to the physical input port. The use of virtual ports allows for flexible wireless design implementations using the same RF transceiver, and in particular, for receive diversity implementations that inherently require dedicated input ports. The use of low cost and small area virtual ports obviates the need for larger and more costly RF receivers.
摘要翻译： 收发器接口架构，其中相同的RF收发器可以在支持任何数量的标准的无线设备中使用，具有或不具有接收分集实现。 RF收发器的每个输入端口可以由多个输入信号共享，这有效地扩展了可用输入端口的数量。 可以通过接收两个或更多输入信号的虚拟端口实现输入端口共享，并选择性地将一个信号传递到物理输入端口。 虚拟端口的使用允许使用相同的RF收发器的灵活的无线设计实现，并且特别地，用于固有地需要专用输入端口的接收分集实现。 使用低成本和小面积的虚拟端口消除了对更大和更昂贵的RF接收机的需要。
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公开(公告)号：US07693236B2
公开(公告)日：2010-04-06
申请号：US09851191
申请日：2001-05-08
IPC分类号： H03K9/00
CPC分类号： H04L27/2332
摘要： An RF receiver apparatus (31) is provided physically separately from a cooperating baseband processor apparatus (32). The RF receiver includes a mixer circuit (33) and an analog IF-to-digital baseband converter (34) formed on an integrated circuit. Sampling frequencies of the analog IF-to-digital baseband converter are controlled by the RF receiver apparatus.
摘要翻译： 与合作的基带处理器装置（32）物理上分开地提供RF接收机装置（31）。 RF接收机包括形成在集成电路上的混频器电路（33）和模拟IF到数字基带转换器（34）。 模拟IF到数字基带转换器的采样频率由RF接收机设备控制。
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公开(公告)号：US20070135076A1
公开(公告)日：2007-06-14
申请号：US11297335
申请日：2005-12-09
申请人： Alan Holden , Jason Jaehnig
发明人： Alan Holden , Jason Jaehnig
IPC分类号： H04B1/26
摘要： A wideband mixer circuit that is flexible and reconfigurable so that several identical wideband mixer circuits may be used in lieu of several fixed narrow-band mixers. Such wideband mixer circuits can be provided in multiples within a chip such that multiple inputs are each within a wide frequency range (i.e., 3 GHz) and may be actively narrowed to any desired frequency range by way of the operation inherent to the circuit architecture. Such a chip supports multiple standards at each input.
摘要翻译： 一种宽带混频器电路，其灵活和可重新配置，使得可以使用几个相同的宽带混频器电路来代替几个固定的窄带混频器。 这样的宽带混频器电路可以在芯片内以多个倍数提供，使得多个输入各自在宽的频率范围（即3GHz）内，并且可以通过电路架构固有的操作而被主动地变窄到任何期望的频率范围。 这样的芯片在每个输入端都支持多种标准。
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公开(公告)号：US20070132623A1
公开(公告)日：2007-06-14
申请号：US11297336
申请日：2005-12-09
申请人： Alan Holden
发明人： Alan Holden
IPC分类号： H03M1/12
CPC分类号： H04B1/30 , H04B1/0028 , H04B1/0032
摘要： A CMOS hybrid analog-digital receiver core where filtering and gain functions are implemented in the digital domain. The analog portion of the receiver core includes standard circuits such as a low noise amplifier for receiving an RF input signal, and a mixer circuit for down-converting the RF input signal to a base band frequency signal. The analog to digital conversion function is provided by a merged ADC filter circuit having a low order filter stage and an ADC stage. The low order filter stage performs low order filtering of the base band signal to reduce dynamic range and clock requirements for subsequent analog to digital conversion the ADC stage. The two circuit stages are considered to be merged since they both consist of an interconnection of identical transconductance cells, where each transconductance cell includes a series of interconnected CMOS inverters.
摘要翻译： CMOS数字接收机芯片，其中滤波和增益功能在数字领域得以实现。 接收机核心的模拟部分包括标准电路，例如用于接收RF输入信号的低噪声放大器，以及用于将RF输入信号下变频为基带频率信号的混频器电路。 模数转换功能由具有低阶滤波级和ADC级的合并ADC滤波电路提供。 低阶滤波器级对基带信号执行低阶滤波，以减少ADC级后续模数转换的动态范围和时钟要求。 两个电路级被认为是合并的，因为它们都由相同跨导单元的互连构成，其中每个跨导单元包括一系列互连的CMOS反相器。
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