公开(公告)号：US20100096695A1

公开(公告)日：2010-04-22

申请号：US12252368

申请日：2008-10-16

申请人： Han Guan Chew ,  Jinping Liu ,  Alex Kh See ,  Mei Sheng Zhou

发明人： Han Guan Chew ,  Jinping Liu ,  Alex Kh See ,  Mei Sheng Zhou

IPC分类号： H01L47/00 ,  H01L21/336

CPC分类号： H01L29/4966 ,  H01L21/31155 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

摘要： A semiconductor device that includes a substrate having an active region prepared with a transistor is presented. The semiconductor device includes a stress structure adjacent to the substrate. The stress structure includes a dielectric layer having nanocrystals embedded therein. The nanocrystals induce a first or a second stress on a channel region of the transistor which improves carrier mobility of the transistor.

摘要翻译： 提出了一种包括具有由晶体管制备的有源区的衬底的半导体器件。 半导体器件包括与衬底相邻的应力结构。 应力结构包括其中嵌有纳米晶体的电介质层。 纳米晶体在晶体管的沟道区域上引起第一或第二应力，这改善了晶体管的载流子迁移率。

公开(公告)号：US08546873B2

公开(公告)日：2013-10-01

申请号：US13241215

申请日：2011-09-23

申请人： Jinping Liu ,  Hai Cong ,  Binbin Zhou ,  Alex Kh See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Hai Cong ,  Binbin Zhou ,  Alex Kh See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L29/66

CPC分类号： H01L21/823468 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.

摘要翻译： 一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物 在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

公开(公告)号：US20110281410A1

公开(公告)日：2011-11-17

申请号：US13190805

申请日：2011-07-26

申请人： JINPING LIU ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： JINPING LIU ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US20090218597A1

公开(公告)日：2009-09-03

申请号：US12040562

申请日：2008-02-29

申请人： Jinping Liu ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US08415236B2

公开(公告)日：2013-04-09

申请号：US12648309

申请日：2009-12-29

申请人： Han Guan Chew ,  Jinping Liu ,  Alex Kai Hung See ,  Mei Sheng Zhou

发明人： Han Guan Chew ,  Jinping Liu ,  Alex Kai Hung See ,  Mei Sheng Zhou

IPC分类号： H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底的第一和第二暴露部分上选择性地形成第一层。 第一和第二暴露部分具有不同的尺寸并且位于第一和第二有源器件附近。 在第一层形成期间，提供了包含用作形成第一层的生长组分的第一和第二源气体和用作控制第一层生长选择性的蚀刻组分的反应气体的气体混合物。 反应物气体与第一和第二源气体不同，并且第一和第二源气体之一与第二暴露部分相比以较快的速率在第一暴露部分上形成第一层，而另一个源气体表现出相反的作用。

公开(公告)号：US20100019329A1

公开(公告)日：2010-01-28

申请号：US12220792

申请日：2008-07-28

申请人： Debora Chyiu Hyia Poon ,  Alex KH See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Debora Chyiu Hyia Poon ,  Alex KH See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L27/088 ,  H01L21/66 ,  G06F17/50

CPC分类号： H01L27/088 ,  H01L27/0211

摘要： A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

摘要翻译： 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。

公开(公告)号：US08293544B2

公开(公告)日：2012-10-23

申请号：US12220792

申请日：2008-07-28

申请人： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/00

CPC分类号： H01L27/088 ,  H01L27/0211

摘要： A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

摘要翻译： 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。

公开(公告)号：US08716076B2

公开(公告)日：2014-05-06

申请号：US13190805

申请日：2011-07-26

申请人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/338

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US08012839B2

公开(公告)日：2011-09-06

申请号：US12040562

申请日：2008-02-29

申请人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US20090053864A1

公开(公告)日：2009-02-26

申请号：US11844074

申请日：2007-08-23

申请人： Jinping Liu ,  Alex K.H. See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K.H. See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02609 ,  H01L29/045

摘要： A method for fabricating a semiconductor structure having heterogeneous crystalline orientations by forming a region including a semiconductor material having a specified crystalline orientation using an epitaxial buffer overlying a semiconductor substrate. The buffer provides a transfer body such that the semiconductor material has a crystalline orientation that differs from the crystalline orientation of a semiconductor region underlying the buffer. The method also includes fabricating a semiconductor structure having a p-type device region and an n-type device region, where a supporting semiconductor substrate is either n-type or p-type and where the semiconductor material is separated from the substrate by a buffer and has a crystalline orientation that differs from the crystalline orientation of the substrate.

摘要翻译： 一种通过使用覆盖在半导体衬底上的外延缓冲层形成包含具有指定结晶取向的半导体材料的区域来制造具有异质结晶取向的半导体结构的方法。 缓冲器提供转移体，使得半导体材料具有不同于缓冲器下面的半导体区域的晶体取向的结晶取向。 该方法还包括制造具有p型器件区域和n型器件区域的半导体结构，其中支持半导体衬底是n型或p型，并且半导体材料通过缓冲器与衬底分离 并且具有不同于衬底的晶体取向的结晶取向。