公开(公告)号：US20080002477A1

公开(公告)日：2008-01-03

申请号：US11836142

申请日：2007-08-09

申请人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

发明人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC分类号： G11C11/34 ,  H01L21/36

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

摘要翻译： 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US08325530B2

公开(公告)日：2012-12-04

申请号：US11542749

申请日：2006-10-03

申请人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Erh-Kun Lai

发明人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Erh-Kun Lai

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7883

摘要： A method of performing an operation on a flash memory cell device, used when a gate coupling ratio between a floating gate and a control gate of less than 0.4. A potential is required to be applied across the control gate. Electrons are either injected to the floating gate from the control gate or ejected from the floating gate to the control gate. The operation associated with the injection or the ejection is determined by the nature of a silicon channel provided in the device. Devices using a bulk-tied FinFET-like structure are particularly suited to this method. The method is also particularly suited for use on cells in a NAND array.

摘要翻译： 在浮动栅极和控制栅极之间的栅极耦合比小于0.4时使用的对闪存单元器件进行操作的方法。 需要在控制门上施加电位。 电子从控制栅极注入到浮动栅极或从浮动栅极喷射到控制栅极。 与注射或喷射相关联的操作由设备中提供的硅通道的性质决定。 使用大容量FinFET类结构的器件特别适用于该方法。 该方法还特别适用于NAND阵列中的单元。

公开(公告)号：US20100311217A1

公开(公告)日：2010-12-09

申请号：US12818057

申请日：2010-06-17

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US07763927B2

公开(公告)日：2010-07-27

申请号：US11300813

申请日：2005-12-15

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US07510924B2

公开(公告)日：2009-03-31

申请号：US11836142

申请日：2007-08-09

申请人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

发明人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC分类号： H01L21/337

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

摘要翻译： 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US07268379B2

公开(公告)日：2007-09-11

申请号：US11162274

申请日：2005-09-05

申请人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

发明人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC分类号： H01L29/80

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

摘要翻译： 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US08481388B2

公开(公告)日：2013-07-09

申请号：US12818057

申请日：2010-06-17

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US20080080248A1

公开(公告)日：2008-04-03

申请号：US11542749

申请日：2006-10-03

申请人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Erh-Kun Lai

发明人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Erh-Kun Lai

IPC分类号： G11C16/04 ,  G11C11/34 ,  H01L29/76

CPC分类号： G11C16/10 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7883

摘要： A method of performing an operation on a flash memory cell device, used when a gate coupling ratio between a floating gate and a control gate of less than 0.4. A potential is required to be applied across the control gate. Electrons are either injected to the floating gate from the control gate or ejected from the floating gate to the control gate. The operation associated with the injection or the ejection is determined by the nature of a silicon channel provided in the device. Devices using a bulk-tied FinFET-like structure are particularly suited to this method. The method is also particularly suited for use on cells in a NAND array.

摘要翻译： 在浮动栅极和控制栅极之间的栅极耦合比小于0.4时使用的对闪存单元器件进行操作的方法。 需要在控制门上施加电位。 电子从控制栅极注入到浮动栅极或从浮动栅极喷射到控制栅极。 与注射或喷射相关联的操作由设备中提供的硅通道的性质决定。 使用大容量FinFET类结构的器件特别适用于该方法。 该方法还特别适用于NAND阵列中的单元。

公开(公告)号：US20070052010A1

公开(公告)日：2007-03-08

申请号：US11162274

申请日：2005-09-05

申请人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

发明人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

摘要翻译： 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US08252654B2

公开(公告)日：2012-08-28

申请号：US12942312

申请日：2010-11-09

申请人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

发明人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66833 ,  H01L29/792

摘要： In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type.

摘要翻译： 在存储单元的制造方法中，设置有基板。 在基板的表面附近形成具有第一导电类型的掺杂区域。 去除衬底的一部分以在衬底中限定多个鳍结构。 在翅片结构之间形成多个隔离结构。 隔离结构的表面低于翅片结构的表面。 栅极结构形成在衬底上并跨越翅片结构。 栅极结构包括跨过鳍结构的栅极和位于鳍结构和栅极之间的电荷存储结构。 源极/漏极区域由栅极结构暴露的鳍状结构中的第二导电类型形成，并且第一导电类型不同于第二导电类型。