公开(公告)号：US08759899B1

公开(公告)日：2014-06-24

申请号：US13739914

申请日：2013-01-11

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

IPC分类号： H01L29/788

CPC分类号： H01L22/12 ,  H01L22/20 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649

摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

摘要翻译： 集成电路器件包括包括第一区域和第二区域的衬底。 在第一区域形成凹坑。 与绝缘层交替的一叠有源层沉积在凹坑中。 堆叠包括特定的绝缘层。 特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。 第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。 该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

公开(公告)号：US20140197516A1

公开(公告)日：2014-07-17

申请号：US13739914

申请日：2013-01-11

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

IPC分类号： H01L21/66 ,  H01L29/06

CPC分类号： H01L22/12 ,  H01L22/20 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649

摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

摘要翻译： 集成电路器件包括包括第一区域和第二区域的衬底。 在第一区域形成凹坑。 与绝缘层交替的一叠有源层沉积在凹坑中。 堆叠包括特定的绝缘层。 特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。 第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。 该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

公开(公告)号：US20120181699A1

公开(公告)日：2012-07-19

申请号：US13024546

申请日：2011-02-10

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yi-Hsuan Hsiao

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L27/11582 ,  H01L27/11578

摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a dielectric element, and a conductive line. The first stacked structure and the second stacked structure are disposed on the substrate. Each of the first stacked structure and the second stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other by only the second dielectric portion. The conductive line is disposed on the stack sidewalls of the first stacked structure and the second stacked structure far from the second dielectric portion.

摘要翻译： 提供了一种半导体结构及其制造方法。 半导体结构包括基板，第一堆叠结构，第二堆叠结构，电介质元件和导线。 第一堆叠结构和第二堆叠结构设置在基板上。 第一堆叠结构和第二堆叠结构中的每一个包括交替堆叠的导电条和绝缘条。 导电条通过绝缘条彼此分离。 电介质元件设置在第一堆叠结构和第二堆叠结构上并且包括第二电介质部分。 第一堆叠结构和第二堆叠结构仅通过第二电介质部分彼此分离。 导电线设置在第一堆叠结构的堆叠侧壁和远离第二电介质部分的第二堆叠结构中。

公开(公告)号：US08304911B2

公开(公告)日：2012-11-06

申请号：US13024546

申请日：2011-02-10

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yi-Hsuan Hsiao

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC分类号： H01L23/48

CPC分类号： H01L27/11582 ,  H01L27/11578

摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a dielectric element, and a conductive line. The first stacked structure and the second stacked structure are disposed on the substrate. Each of the first stacked structure and the second stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other by only the second dielectric portion. The conductive line is disposed on the stack sidewalls of the first stacked structure and the second stacked structure far from the second dielectric portion.

摘要翻译： 提供了一种半导体结构及其制造方法。 半导体结构包括基板，第一堆叠结构，第二堆叠结构，电介质元件和导线。 第一堆叠结构和第二堆叠结构设置在基板上。 第一堆叠结构和第二堆叠结构中的每一个包括交替堆叠的导电条和绝缘条。 导电条通过绝缘条彼此分离。 电介质元件设置在第一堆叠结构和第二堆叠结构上并且包括第二电介质部分。 第一堆叠结构和第二堆叠结构仅通过第二电介质部分彼此分离。 导电线设置在第一堆叠结构的堆叠侧壁和远离第二电介质部分的第二堆叠结构中。

公开(公告)号：US20120220111A1

公开(公告)日：2012-08-30

申请号：US13463264

申请日：2012-05-03

申请人： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

发明人： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

IPC分类号： H01L21/04

CPC分类号： H01L29/665 ,  G11C16/0408 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

摘要翻译： 描述了具有肖特基源和漏极的非易失性存储单元的注入方法。 载流子注入效率由硅化物和硅的界面特性控制。 通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

公开(公告)号：US20120181684A1

公开(公告)日：2012-07-19

申请号：US13009502

申请日：2011-01-19

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC分类号： H01L23/48 ,  H01L21/31

CPC分类号： H01L23/485 ,  H01L24/64 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/792

摘要： A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.

摘要翻译： 提供半导体结构及其制造方法。 该方法包括以下步骤。 在基板上形成第一含硅导电材料。 在第一含硅导电材料上形成第二含硅导电材料。 第一含硅导电材料和第二含硅导电材料具有不同的掺杂条件。 第一含硅导电材料和第二含硅导电材料被热氧化，以将第一含硅导电材料完全转变成绝缘氧化物结构，第二含硅导电材料变成含硅导电结构， 绝缘氧化物层。

公开(公告)号：US20100176438A1

公开(公告)日：2010-07-15

申请号：US12553758

申请日：2009-09-03

申请人： HANG-TING LUE ,  Yi-Hsuan Hsiao

发明人： HANG-TING LUE ,  Yi-Hsuan Hsiao

IPC分类号： H01L27/115

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/513

摘要： A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.

摘要翻译： 存储器件在衬底上包括多个半导体线，例如体结翅片。 这些线包括掺杂用于耗尽模式操作的掩埋沟道区。 存储结构位于多条线上，包括鳍状物的沟道区上的隧道绝缘层，隧道绝缘层上的电荷存储层，以及电荷存储层上的阻挡绝缘层。 多个字线覆盖在存储结构上并与半导体线的沟道区交叉，由此存储单元位于字线和半导体线的交叉点。

公开(公告)号：US08860124B2

公开(公告)日：2014-10-14

申请号：US12553758

申请日：2009-09-03

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC分类号： H01L29/66 ,  H01L27/115 ,  H01L29/51 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/513

摘要： A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.

摘要翻译： 存储器件在衬底上包括多个半导体线，例如体结翅片。 这些线包括掺杂用于耗尽模式操作的掩埋沟道区。 存储结构位于多条线上，包括鳍状物的沟道区上的隧道绝缘层，隧道绝缘层上的电荷存储层，以及电荷存储层上的阻挡绝缘层。 多个字线覆盖在存储结构上并与半导体线的沟道区交叉，由此存储单元位于字线和半导体线的交叉点。

公开(公告)号：US08183617B2

公开(公告)日：2012-05-22

申请号：US12430817

申请日：2009-04-27

申请人： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

发明人： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

IPC分类号： H01L29/76

CPC分类号： H01L29/665 ,  G11C16/0408 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

摘要翻译： 描述了具有肖特基源和漏极的非易失性存储单元的注入方法。 载流子注入效率由硅化物和硅的界面特性控制。 通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

公开(公告)号：US20100172183A1

公开(公告)日：2010-07-08

申请号：US12540260

申请日：2009-08-12

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/4234 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568

摘要： With advanced lithographic nodes featuring a half-pitch of 30 nm or less, charge trapping NAND memory has neighboring cells sufficiently close together that fringing fields from a neighboring pass gate interferes with the threshold voltage. The interference results from fringing fields that occupy the gaps that separate the neighboring charge storage structures. The fringing electric fields are suppressed, by the insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide, from entering the neighboring charge storage structures. In some embodiments, the insulating structures suppress the fringing electric fields from entering a channel region. This suppresses the short channel effects despite the small dimensions of the devices.

摘要翻译： 利用具有30nm或更小的半间距的先进光刻节点，电荷捕获NAND存储器具有足够靠近的相邻单元，来自相邻通孔的边缘场干扰阈值电压。 干扰源于占据隔离相邻电荷存储结构的间隙的边缘场。 通过相对于小于氧化硅的相对介电常数的真空的相对介电常数的绝缘结构，边缘电场被抑制，从而进入邻近的电荷存储结构。 在一些实施例中，绝缘结构抑制边缘电场进入沟道区域。 尽管设备的尺寸较小，但这抑制了短通道效应。