摘要:
A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.
摘要:
Process of making a semiconductor using dual inorganic hardmask in single damascene process integration scheme in an organic low k interlayer dielectric (ILD) by: providing semiconductor substrate; depositing organic low k ILD layer on substrate; forming hardmask 1 on organic low k ILD layer and forming sacrificial hardmask 2 on hardmask 1; forming a patterned photoresist layer on sacrificial hardmask 2; etching selective to sacrificial hardmask 2 and stripping photoresist; etching of hardmask 1 in which the etch is selective to the organic low k ILD layer; depositing a liner or conformal barrier layer over the substrate, organic low k ILD layer, hardmask 1 and hardmask 2; forming a plated metal layer over the liner or conformal barrier layer; and removing metal layer and removing liner with simultaneous removal of sacrificial hardmask 2 so that facets in sacrificial hardmask 2 are removed during liner/sacrificial hardmask 2 removal.
摘要:
Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.
摘要:
The invention concerns a method and device for checking tightness of containers, housings and similar test objects (15). The test object (15) is subjected to a pressurized test gas. If a leak (28) is present, test gas escapes from the text object (15) and is exposed in a test chamber (18) to an intensity-modulated electromagnetic wave field emitted by a laser (1). The wave field contains frequency components which are absorbed by the test gas to produce a photo-acoustic signal indicative of the presence of a leak. To facilitate a quantitative tightness examination even using a longitudinal multimode laser with several laser modes which can be absorbed by the test gas, it is proposed according to the present invention that the temperature of the laser (1) should be set to a reference value and the excitation power of the laser should be kept at a constant mean level, so that the photo-acoustic signal can be measured and evaluated as a measure of the test gas concentration in the test chamber and/or of the size of the leak from the test object. To improve measuring accuracy, a reference chamber (5) with a predetermined test gas concentration is in addition exposed to the intensity-modulated wave field emitted by the laser (1); the photo-acoustic signal (6) produced in the reference chamber (5) is then used either for standardization purposes for when the test gas concentration in the test chamber (18) is determined, or for adjusting the reference temperature value (T.sub.ref) of the laser (1) to a predetermined working point.
摘要:
A masking arrangement and method for producing integrated circuit. arrangements are described. The masking arrangement includes a substrate with lithographic patterns. The lithographic patterns are arranged in different partial regions for integrated circuits that have mutually different wiring of components as well as for test patterns. Auxiliary patterns are provided for alignment of multiple lithography planes during production of one of the circuit arrangements either with or without simultaneous production of another of the circuit arrangement. The auxiliary patterns are arranged close to corners of each of the partial regions and contain alignment or overlap marks. The auxiliary patterns and the test pattern for a particular partial region form a frame around the partial region. Filling patterns are present between the partial regions.
摘要:
A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.
摘要:
An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.
摘要:
A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack on a semiconductor substrate, and forming a protective layer on sidewalls of the gate stack. The protective layer extends horizontally over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer is formed over the protective layer and in contact with a gate conductor of the gate stack and in contact with a diffusion region formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor. The exposed areas of the conductive layer are silicided to form a direct buried strap and a silicided diffusion region in the substrate. The direct buried strap electrically connects the gate conductor to the diffusion region in a same level of the semiconductor device.