公开(公告)号：US06559042B2

公开(公告)日：2003-05-06

申请号：US09894337

申请日：2001-06-28

申请人： Hans-Joachim Barth ,  Lloyd G. Burrell ,  Gerald R. Friese ,  Michael Stetter

发明人： Hans-Joachim Barth ,  Lloyd G. Burrell ,  Gerald R. Friese ,  Michael Stetter

IPC分类号： H01L213205

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

公开(公告)号：US06908841B2

公开(公告)日：2005-06-21

申请号：US10251453

申请日：2002-09-20

申请人： Lloyd G. Burrell ,  Douglas Kemerer ,  Henry A. Nye, III ,  Hans-Joachim Barth ,  Emmanuel F. Crabbe ,  David Anderson ,  Joseph Chan

发明人： Lloyd G. Burrell ,  Douglas Kemerer ,  Henry A. Nye, III ,  Hans-Joachim Barth ,  Emmanuel F. Crabbe ,  David Anderson ,  Joseph Chan

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low modulus dielectric layers (216, 222, 232) are disposed over a workpiece (212). Support structures (218, 226, 236) are formed in the low modulus dielectric layers (216, 222, 232), and support vias (224, 234) are formed between the support structures (218, 226, 236). A high modulus dielectric film (220, 230) is disposed between each low modulus dielectric layer (216, 222, 232), and a high modulus dielectric layer (256) is disposed over the top low modulus dielectric layer (232). Contact pads (204) are formed in the high modulus dielectric layer (256). Each support via (234) within the low modulus dielectric layer (232) resides directly above a support via (224) in the underlying low modulus dielectric layer (222), to form a plurality of via support stacks within the low modulus dielectric layers (216, 222, 232).

摘要翻译： 一种在接触焊盘（204）的引线键合区域（214）下方具有支撑结构（218,226,236）的半导体器件（200）及其形成方法。 低模量介电层（216,222,232）设置在工件（212）上方。 支撑结构（218,226,236）形成在低模量电介质层（216,222,232）中，并且支撑通孔（224,234）形成在支撑结构（218,226,236）之间。 高模量介电膜（220,230）设置在每个低模量介电层（216,222,232）之间，并且高模量介电层（256）设置在顶部低模量介电层（232）之上。 接触焊盘（204）形成在高模量介电层（256）中。 在低模量介电层（232）内的每个支撑件（234）直接位于下面的低模量介电层（222）中的支撑通孔（224）的上方，以在低模量介电层（222）内形成多个通孔支撑堆叠 216,222,232）。

公开(公告)号：US07867820B2

公开(公告)日：2011-01-11

申请号：US12121468

申请日：2008-05-15

申请人： Lloyd G. Burrell ,  Howard Hao Chen ,  Louis L. Hsu ,  Wolfgang Sauter

发明人： Lloyd G. Burrell ,  Howard Hao Chen ,  Louis L. Hsu ,  Wolfgang Sauter

IPC分类号： H01L21/00

CPC分类号： H01L23/5389 ,  H01L21/52 ,  H01L23/147 ,  H01L23/5385 ,  H01L2221/68322 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/00

摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

摘要翻译： 提出了用于形成共面多芯片晶片级封装的经济方法。 部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。 然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。 所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。 不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。 由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，这消除了将芯片从倒置位置翻转的需要。

公开(公告)号：US07037824B2

公开(公告)日：2006-05-02

申请号：US10844533

申请日：2004-05-13

申请人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

发明人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

公开(公告)号：US06960831B2

公开(公告)日：2005-11-01

申请号：US10605369

申请日：2003-09-25

申请人： Lloyd G. Burrell ,  Kwong H. Wong ,  Adreanne A. Kelly ,  Samuel R. McKnight

发明人： Lloyd G. Burrell ,  Kwong H. Wong ,  Adreanne A. Kelly ,  Samuel R. McKnight

IPC分类号： H01L23/485 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L23/53223 ,  H01L24/45 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device, and a method of fabricating the device, having a copper wiring level and an aluminum bond pad above the copper wiring level. In addition to a barrier layer which is normally present to protect the copper wiring level, there is a composite layer between the aluminum bond pad and the barrier layer to make the aluminum bond pad more robust so as to withstand the forces of bonding and probing. The composite layer is a sandwich of a refractory metal and a refractory metal nitride.

摘要翻译： 一种半导体器件，以及一种制造该器件的方法，在铜布线层上方具有铜布线层和铝接合焊盘。 除了通常存在以保护铜布线水平的阻挡层之外，在铝接合焊盘和阻挡层之间存在复合层，以使铝接合焊盘更坚固，以便承受粘结和探测的力。 复合层是难熔金属和难熔金属氮化物的夹层物。

公开(公告)号：US07294565B2

公开(公告)日：2007-11-13

申请号：US10676172

申请日：2003-10-01

申请人： Lloyd G. Burrell ,  Charles R. Davis ,  Ronald D. Goldblatt ,  William F. Landers ,  Sanjay C. Mehta

发明人： Lloyd G. Burrell ,  Charles R. Davis ,  Ronald D. Goldblatt ,  William F. Landers ,  Sanjay C. Mehta

IPC分类号： H01L21/28 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L23/53223 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/0501 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/45124 ,  H01L2224/48744 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48

摘要： A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.

摘要翻译： 提供了一种通过能够防止在Ni / Au焊盘冶金的无电沉积期间可能的化学侵蚀的材料来密封引线接合焊盘的暴露表面的方法。 具体地说，本发明提供了一种TiN / Ti或TiN / Al帽作为覆盖引线接合焊盘露出表面的保护涂层的方法。 TiN / Ti或TiN / Al帽不受用于形成Ni / Au金属化的碱性化学物质的影响，但它提供了将接合焊盘连接到Ni / Au焊盘金属化的足够的电通路。

公开(公告)号：US07250311B2

公开(公告)日：2007-07-31

申请号：US10906507

申请日：2005-02-23

申请人： Toyohiro Aoki ,  Lloyd G. Burrell ,  Wolfgang Sauter

发明人： Toyohiro Aoki ,  Lloyd G. Burrell ,  Wolfgang Sauter

IPC分类号： H01L21/66 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L22/34 ,  H01L24/02 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00

摘要： A sensor for measuring cracks in a semiconductor device, such as a wafer and, more particularly, to a BEOL wirebond crack sensor for low-k dies or wafers, and a method of providing the wirebond crack sensor for low-k wafers or the like structures.

摘要翻译： 用于测量诸如晶片的半导体器件中的裂纹的传感器，更具体地，涉及用于低k晶片或晶片的BEOL引线接合裂纹传感器，以及为低k晶片等提供引线接合裂纹传感器的方法 结构。

公开(公告)号：US20080280399A1

公开(公告)日：2008-11-13

申请号：US12121468

申请日：2008-05-15

申请人： Lloyd G. Burrell ,  Howard Hao Chen ,  Louis L. Hsu ,  Wolfgang Sauter

发明人： Lloyd G. Burrell ,  Howard Hao Chen ,  Louis L. Hsu ,  Wolfgang Sauter

IPC分类号： H01L21/00

CPC分类号： H01L23/5389 ,  H01L21/52 ,  H01L23/147 ,  H01L23/5385 ,  H01L2221/68322 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/00

摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

摘要翻译： 提出了用于形成共面多芯片晶片级封装的经济方法。 部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。 然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。 所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。 不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。 由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，这消除了将芯片从倒置位置翻转的需要。

公开(公告)号：US07405108B2

公开(公告)日：2008-07-29

申请号：US10994494

申请日：2004-11-20

申请人： Lloyd G. Burrell ,  Howard Hao Chen ,  Louis L. Hsu ,  Wolfgang Sauter

发明人： Lloyd G. Burrell ,  Howard Hao Chen ,  Louis L. Hsu ,  Wolfgang Sauter

IPC分类号： H01L21/00

CPC分类号： H01L23/5389 ,  H01L21/52 ,  H01L23/147 ,  H01L23/5385 ,  H01L2221/68322 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/00

摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

摘要翻译： 提出了用于形成共面多芯片晶片级封装的经济方法。 部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。 然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。 所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。 不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。 由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，从而不需要将芯片从倒置的位置翻转。

公开(公告)号：US07087997B2

公开(公告)日：2006-08-08

申请号：US09805027

申请日：2001-03-12

申请人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

发明人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.